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i have written an AND GATE PROGRAM FOR PAPILLIO PRO SYNTHESISING AND BIT FILE GENERATION COMPLETED SUCCESSFULLY.INPUT a and b are used as switches.output c is LED.no led's are blinking while i change the switch.whate is the speed grade to be selected -2 or -3? vhdl code and ucf are given below..please give a soln library ieee; use IEEE.STD_LOGIC_1164.ALL; entity And_Gate is port(a,b:in std_logic; c:out std_logic); end entity And_Gate; architecture And_Gate_Arch of And_Gate is begin c<=a and b; end And_Gate_Arch; CONFIG PROHIBIT=P144; CONFIG PROHIBIT=P69; CONFIG PROHIBIT=P60; NET "a" LOC="P114" | IOSTANDARD=LVTTL; # C0 NET "b" LOC="P115" | IOSTANDARD=LVTTL; # C1 NET "c" LOC="P123" | IOSTANDARD=LVTTL;