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  1. I had a VHDL question for any of the gurus out there. I am sure the issue is my mindset coming from a software background. Hopefully someone can set me straight. I am trying to understand some Xilinx AXI bus code that seems to process the AXI registers in a submodule of the top module. Say I have a top level module and another sub module that is instantiated from the top level module. The sub module has ports for a bus and one or more registers. entity submod port ( controlReg0 --Register to send control signals statusReg1 --register to return current operating status bus -- multiple bus signals but just being high level here ); Internally this sub module processes bus signals and stores register updates that come over the bus to the registers In the top module entity topmodule port( bus --multiple bus signals but just being high level here ); Now within the top module code there are signals say reg0 and reg1 defined. Within the top module code it instantiates the submodule like so. test : submod port map ( reg0 => controlReg0, reg1 => statusReg1, bus=>bus ) In this scenario are the reg0 in the top module and the controlReg0 in the submodule actually the same or are they 2 different actual entities. What I mean is when some data is sent over the bus and the value of controlReg0 is changed in the submodule is the value of reg0 also changed or do I need to do a specific assignment? And vice versa if the value of reg0 is changed in the top level module is that value reflected in the next read of the controlReg0 over the bus? I think it looks like they are just 2 different references to the same register since in the port I set then to be the assigned to each other, but I could be way off here. Not sure how this is all handled once it is translated to hardware. Any insight would be helpful. Thanks, Chris