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Showing results for tags 'DCM'.
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I read the tutorial and it makes sense, I created the DCM using the clock wizard but can't get the code to compile. I get an error "ERROR:Xst:2035 - Port <clk> has illegal connections. This port is connected to an input buffer and other components.". Does anyone know what I need to do to correct the error? Does anyone have an example of code that compiles and works? myDCM.vhd
Hello, I recently ran into a problem driving multiple DCM's from a single external clock source. Ive looked around for solutions and become familiar with Xilinx's documentation for the Spartan's DCM layout. The problem is that you cannot drive more than one DCM from the same external signal because when mapping it will try to duplicate the input clock buffer . The solution is that you must buffer the external signal using IBUF and specifiy the DCMs to be driven by this internal signal. I've implemented a buffer to do this  and drive each DCM with this buffered signal. However, I still run into mapping errors when compiling the project. I am not on a computer with my source code or mapping errors at the moment, however I wanted to see if anyone had any insight about this. References:  http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Two-parallel-DCMs-on-Spartan3e/td-p/182856  http://www.cs.indiana.edu/hmg/le/project-home/xilinx/ise_8.1/doc/usenglish/de/libs/lib/ibuf4816.pdf