Search the Community: Showing results for tags 'CPU'.
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Hey guys, I am developing a new CPU (for fun and beyond), which aims to replace the slow ZPU we have been using so far. The new CPU design is coming along very well, and should match and eventually outperform the Xilinx Microblaze in program size, performance (MHz) and implementation size (well, perhaps this one not, let's see). The CPU is 32-bit, RISC-like, with 31 general purpose registers, a zero register, and a few special registers. It's an hybrid of well known CPUs, like Microblaze, ARM, SPARC, and others. All instructions are 16-bit, and can be extended for immediate values. It has 2 to 5 asymmetric ALU, which in certain scenarios allows the CPU to execute two (or more) instructions at the same time. All normal addressing modes are supported. The design uses 3 to 6 pipeline stages, depending on configuration. All branch instructions have delay slots. The objective is to have a fast CPU (something between 100MHz and 166Mhz) , superscalar, and have it fit nicely on a PPro/Papilio One while using the same Wishbone interface as ZPUino does. The current state is: it works in simulation, an assembler/linker is already working, still missing the C/C++ compiler (LLVM), Now... I really need to name it. And this is where I need your advice and help. The best name I found so far is "XThunderCore", or abbreviated, "XTC". What are your ideas ? Can you come up with a better name for it ? Best, Alvie
I was updating my LLVM tree today (long time since I did it) to prepare for XThunderCore SmallISA, and I found a new CPU in there, called "Lanai". A quick search returned some info - this CPU seems to be in development by Google , and it's similar to a microcontroller but aimed at massive parallel computations. Did not have time to explore much - looks like a classical RISC to me ythough. You can get a glimpse of the instruction formats by looking at the LLVM implementation: https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Lanai/LanaiInstrFormats.td Any of you ever heard of this, and if any soft-core implementation is available in the wild ? Magnus ? (I will update you guys regarding the XThunderCore SmallISA in a couple of weeks). Alvie  https://www.phoronix.com/scan.php?page=news_item&px=Google-Lanai-Architecture  http://www.theregister.co.uk/2016/02/09/google_processor/  http://lists.llvm.org/pipermail/llvm-dev/2016-February/095118.html