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Papilio Duo. Have Windows 10, for which the only ISE available is a virtual machine that runs on Oracle VM. I can run designLab on Win 10 and it will load AVR programs, but not FPGA. I cannot figure out how ISE on the VM would communicate with the DesignLab on Win 10. I have tried that VM, and cannot seem to get it to talk to the host machine USB interface. (some kind of libftdi problem) Can run DesignLab on Win 10 - but it won't load to the FPGA/ZPUino. Ran Windows 7 as a VM - it also will not talk to the USB-just hangs during upload. Has anyone found a combination that works for Windows 10, and allows FPGA to be loaded, (even just the Duo Quickstart example)?

A cool project about a camera driver on a Zedboard fpga running Petalinux streaming live images to a client PC via TCP sockets . Check out the project and source code here !!

An LCD driver for the most common lcd controller to be used in fpgas and not only ... Check out the project and code here!!

Me and a partner created a version of the classic Space invaders arcade game in a Zedboard FPGA 100 % in Verilog. Check out the project and code here !!

I have heard about this FPGA company. They have two development boards yet they are not open source. So my question is: Can anyone please make a open source non-volatile FPGA board? http://www.gowinsemi.com.cn/en/kaifa.aspx

Hi, I'm writing a serial SRAM-interface between AVR and the SRAM available to the FPGA. Aim is to learn VHDL/FPGA programming so I'm not taking easiest route here. But I have a problem! I now have a small program on the AVR-side that transmits ones and zeroes to the fpga at a very low rate (say one per second now during debug). I'm using the MOSI-pin for this. When switching from 0 to 1 I detect _one_ rising edge on the fpga (by tracking value from last clock and current clock and looking for a 0->1 transition). When switching from 1 to 0 I detect _multiple_ rising edges on the fpga. There should be none. My question is if the AVR outputs correct nice digital signals that are interpreted as ones and zeros on the fpga, or do I need to process them somehow? Is there something special about the MOSI pin? All my VHDL programs looks fine during simulation so now I'm looking at other external factors. My VHDL program is still under suspicion of course! Thanksful for any help I can get!

note: Solved, the problem might have been related to having the incorrect board selected. Hi, I'm trying to communicate between the AVR (hard core) processor and the fpga. I've verified that AVR works. I can do serial, blink LED 13 etc, blink LEDs on my breadboard etc. However I'm having troubles "connecting" one of the AVR-compatible pins to a FPGA-pin. Would be happy for any help I could get! I'll be happy to make a tutorial/example once I figure all of this out Details: I'm opening a pin (using pinMode) on the AVR side as an output. I'm accessing that same pin in my ISE schematics and just routing it to an output (say Arduino_40). I've tried different pins (with 0-14 as output from AVR and all the CH-wing pins as outputs). My schematics has no zpuino, all there is what you can see from ise.png plus the AVR disable/enable bit. In order to route an input directly to an output I had a to make a really simple VHDL-snippet that just routes the value. See breakin_passthrough.vhdl. The problem might be in me misunderstanding how this is supposed to work. Sidenote: I'm avoiding wishbone since it relies on zpuino and I want the SRAM all to myself in the fpga. In my sketch I do void setup() { pinMode(13, OUTPUT);} and in loop I do void loop() { digitalWrite(13, HIGH); delay(500); digitalWrite(13, LOW); delay(500); } I've chosen 13 so I can see the LED blink when it is running, but I've tried other ones as well. Thanks again! ps. See this thread http://forum.gadgetfactory.net/index.php?/topic/2415-communication-zpuinofpga/for a discussion on what I'm trying to do and why I want to avoid the zpuino for now.breakin_passthrough.vhd

Hi! I've just recently received my DUO board and I have some beginners questions! First let me say that I'm super happy with it so good work everyone! Falling importance! 1) I've successfully done some zpuino stuff as well as some fpga stuff. I'm looking for a real simple way to communicate between zpuino and fpga. For now I would be happy if the zpuino could set a bit (when all init is ready) and then I could access it in my ISE schematics somehow. If this was running on the AVR I would go via an external pin, but that feels wrong now that I'm completely in fpga land! I've read a little about the wishbone concept but I was hoping I could postpone using it for a little bit. I mostly want simple internal GPIO. Am I missing something simple? 2) I've used malloc to grab a SRAM-memory block in the zpuino. I was wondering if there was a function get a block located at a certain place? I would want to use it to make sure that the zpuino never uses the memory. Something like. unsigned char *a = (unsigned char*)placed_malloc(position, size); That way I can _assume_ where my memory is located at, and the zpuino can malloc as much as it wants without stealing my memory. 3) Is there a way to connect an input directly to an output in an ISE schematics editor? Are there symbols that represent logic high / logic low? Thanks!

http://www.nxlab.fer.hr/fpgarduino/ The FPGArduino project provides pre-built software tools and FPGA configuration bitstreams which transform popular FPGA development boards into microcontroller systems programmable using the intuitive Arduino development environment. https://github.com/f32c/arduino If you like it you can support it by adding support for your board...

Hi everyone, I just ordered my first Papillio FPGA ! I am continuing a (huge) project that I started based on the Cyclone V GX starter kit from Terassic. I had a hard time finding documentation and support online and decided to move to Papillio. As a Computer Science Engineering student at EPFL (Switzerland), I have had numerous courses that cover various aspects of computer science/engineering. All those courses felt separated. I decided that I wanted to "fill the gaps" in my knowledge of computers. The ultimate goal is to create a tutorial / source code where one can learn practical computer engineering (I'll include links to good theory books/tutorials/articles). I want to cover the following aspects of computer science: - How the hardware works. (Simple multi/cycle multi-core CPU, no caches), VGA, Serial, keyboard, other peripherals (leds ect). - How assembly works - How a compiler works, C-like language design - How a kernel works - How to internet works, either using a computer as proxy (through UART) or if I can find an opensource Ethernet implementation directly from the FPGA. - Writing a simple web-server - Writing some basic javascript The idea is to have for each section: - Some background information - Links to deper / more complex issues (eg: caches, complex theory) - A guided practical "let's do it" I think this covers most of what one needs to know (if you add calculus ) to become a computer scientist. If anyone is interested in the project, I'd be more than happy to do work together ! I currently have: - An assembler / begining of compiler written in F# (I target mono) giving the oportunity to learn functional programming. - http://github.com/OzieGamma - Some VHDL for my CPU. You can find me online: http://beglobal.me

View File Papilio DesignLab IDE We live in exciting times where we can create masterpieces with the Arduino and marvels with the Raspberry Pi. Where we can use technology as a canvas to create things that amaze and amuse our friends and family. Wouldn't it be great if we could take the same technology that has been the staple of rocket scientists and put it in our creative arsenal? Without the need tobecome a rocket scientist or the headache of learning a new programming language like VHDL/Verilog. Why can't we just draw up the circuits that we want to use? With the right software and circuit libraries we can! Let's put a full circuit lab on a chip, pair it with an easy to use Arduino-Compatible chip, and sprinkle in a generous helping of debugging tools. Our dream is to take the hardcore out of FPGA (Field Programmable Gate Array) and make it an amazing tool that anyone can use for creative technology projects. Just like the Arduino team simplified C++ programming, we simplify FPGA design by providing easy to use drag and drop circuit libraries. We believe that drawing circuits will result in an amazing outpouring of creative FPGA projects! We start with the Arduino IDE (Integrated Development Environment) and supercharge it by adding circuits into the mix. We bring all of the pieces needed to draw and debug your very own circuits in one place. It's an easy and seamless user experience that we call Papilio DesignLab for use with both Windows and Linux. Want to get into more complex circuits? DesignLab includes the ZPUino Soft Processor with a Wishbone bus, providing greater speed and flexibility than the Arduino-Compatible chip. A Soft Processor runs inside the FPGA and uses the Wishbone bus to make it easy to connect peripheral circuits, such as UARTs, PWMs or SPI masters. Making your own Soft Processor with just the right mix of peripheral circuits is known as a SOC (System On Chip) design. With DesignLab you can draw your SOC designs in minutes! Create SOCs with ten serial ports, or a PWM on every pin, or something exotic like classic Atari and Commodore audio chips connected at the same time. The sky is the limit, you can create things that don't exist anywhere else! DesignLab Circuit Library Drawing circuits can only accomplish so much without a library of circuits (known as cores) to do the heavy lifting. Our goal is to provide the framework for anyone to write a core that can be wired into a circuit. We want to seek out the best open source circuits on the interwebs and convert them to a dead simple schematic library. The internet is absolutely full of open source circuits; just take a look at sites like OpenCores.com. You will find everything from classic audio chips to stepper motor controllers. All of these amazing circuits are within our reach when converted to schematic form and included with DesignLab IDE! Submitter Jack Gassett Submitted 01/12/2015 Category Papilio FPGA  

Hello I have a Problem i have a DAC that is controlled by the Papilio one 250k. I have a 512 byte array with a sine wave stored in it and I read the array to a IO port. Now the problem: It works most of the time if I programm it only to the FPGA. By working I mean that i can see a beautiful sine wave at the oszi. If I programm it several times it works not always, but the programming of the FPGA is so quick I can try until it works. If it doesn't work the wave form is periodic, not a sine tough. But this tells me that the read of the array works but not the write. If I programm the SPI flash it doesn't work and I get a wave form but it isn't a sine at all. I initalize the array a such: type memory_t is array(0 to 511) of std_logic_vector(7 downto 0);-- Declare the RAMsignal ram_bank : memory_t;and i access it as so: -------------------------------------------------------------------------- write Portprocess(clk_200)begin if(falling_edge(clk_200)) then if(w_en = '1') then ram_bank(to_integer(unsigned(add_w))) <= ram_in; end if; end if;end process; -------------------------------------------------------------------------- read Portprocess(clk_200)begin if(rising_edge(clk_200)) then if(r_en = '1') then ram_out <= ram_bank(to_integer(unsigned(add_r))); end if; end if;end process;I tried to run both processes at the rising edge but this doesn't work at all. The read and write is controlled by a FSM, there is never a read and write at the same time. As you can see I use the ram at 200MHz, is this to fast? I use a microblaze MCS to controll the hole thing, so the MCS has the array static in it and writes it to the dac controller fsm, it stores it in the array and after that it is read periodical. If anyone has a clue. Ohm dac_man.vhd

Hi There, Currently I have been set this project, I am really struggling with how to get going with it. If anyone can assist I would be greatly appreciated. It was a year since I have completed any work in VHDL. If anyone can assist we have been provided with PS2_DISPLAY.vhd, PS2_EXP.ucf, utils.vhd, VHDL_Template_entity.vhd, VHDL_Template_TB.vhd All files are below any help is greatly appreciated! Please assist, thanks in advance. Regards PS2_DISPLAY.vhd utils.vhd VHDL_Template_Entity.vhd VHDL_Template_TB.vhd MiniProject_15.doc PS2_EXP.zip

Hello, Im having a problem with the wishbone interface on the ZPUino soft processor. I am trying to output a signal to a design I have made, in this instance its outputting a reset signal but the same problem occurs on all the other outputs too. The signal and corresponding pin I have the oscilloscope connected to is highlighted in red in fig 1. This goes to a custom block that builds individual signals into a bus that is outputted using the Papilio block set provided, this can be seen in fig 2. Im using the standard ZPUino programing IDE, when I program it to output 0xff to wishbone Register 2 the output pin on the FPGA becomes high, this is shown in figure 3. This is exactly what you would expect to happen. Again in fig 4 the when Register 2 is set to be 0x00 then the output on the pin connected to the oscilloscope is set to logic 0, as expected. However in figure 5 Wishbone register 2 is set to be 0x00 for 100ms then set to 0xff for 200ms, this should produce a waveform that shows a signal that is high twice as long as low. Though this is the comes out as the opposite, it seems that the signal is being inverted. I can’t for the life of me work out why this is. Similarly in fig 6 I set it to be the opposite 0xff for 200ms and 0x00 for 100ms and it does the same, inverting the signals again. I have checked for sources of error in other places, the oscilloscope is working fine Ive tried connecting the Wishbone output directly to a pin to see if the Papilio output block was the cause this had no effect, I’ve double checked my Wishbone interface code its fine no reason to invert the output. This also happens when the delay is increased to 20secconds and 10secconds to see if it was a timing issue and needed a steeling time, keeps inverting the signals still. The weird thing is that it works fine when the is no periodic signal applied and its just a DC output, if it was an inverter causing the problem that’s fine all I need to do is change my code around a bit but this is not that simple and I couldn’t work with an unpredictable output. Does anyone have any suggestion as to what the problem is? Many thanks Joe

Hello, I am brand new to FPGAs and am trying to 1) learn about FPGAs and 2) save an image from a camera to an SD Card using FPGAs. The goal is to use this as a stepping stone to develop a stand-alone aerial imaging system for Quadcopters, aircrafts, etc. Thank you for taking the time to read this, and please excuse me for my novice comments. I am having trouble finding a project that goes through the details of writing an image from a camera module much like the ov7670 (link below) to the MicroSD Wing (link below) using a Papillo board. If you know of any projects that are in anyway similar, could you forward them? Also, I am planning on ordering the Papillo One board and a few wings so I can learn by doing. If you have any recommendations on specific hardware that would be beneficial for my goal, I would love your input. ov7670: http://www.electrodragon.com/product/ov7670-camera-module-breakout-board-power-cable/ MicroSD Wing: http://papilio.cc/index.php?n=Papilio.MicroSDWing Just to say it, I am planning on working this project and updating my status to this forum in case anyone else is interested. Open Source all the way. Thank you guys! -CB

Hi, I may have not dug enough into the Papilo FPGA cards documentation yet, so I am asking here: What about removing the clock? to work in asynchronous mode. How difficult is this with the different cards (I am yet considering buying the Papilio Pro, but answers for the other cards are also welcomed). Does anyone already did it? For information, I am trying to reproduce some results of Dr. David Rosin from Duke University / Technische üniversität Berlin (http://fds.duke.edu/db/aas/Physics/researchers/dpr12), so I really need this asynchronous mode. And I would not go for proprietary devices Best, Julien

I recently purchased this bundle from gadget factory. http://store.gadgetfactory.net/retrocade-megawing-bundle/ I am new to FPGAs but I have coded with Arduinos before. I understand that FPGAs are alot more useful since then can do operations in parallel as opposed to sequences (arduinos; which is why i purchased it). How can I use the ADC of the megawing? Ideally I have two analog inputs, which sample at the same frequency (250hz). I would then like to output this on a graph (maybe serial port on the computer? or a TFT screen?) Can some one show me to the right direction? Thanks.

File Name: Papilio Schematic Library File Submitter: Jack Gassett File Submitted: 29 Oct 2013 File Category: Papilio FPGA A library of Soft Processors and peripherals that can be used with Webpack schematic editor to build a custom SOC for the Papilio. Click here to download this file

Hi guys! I'm just wondering if there's any way to use the programmer on the Papilio to program other devices via JTAG? If there's any, how? I'd probably like to program some Xilinx CPLD, like the XC95144XL with it... I guess it should be possible somehow... Thank you for your answers. Richard, the crazy one.

If I program my Papilio Pro + LogicStart to only use the LEDs and switches (leaving everything else unused and omitted from the UCF per other advice here) I notice that all segments of the 7-segment displays glow dimly once it's programmed and active. I wonder: would it be better to set all unused I/O lines to high-impedance to prevent this side-effect - or is that already the default, and I need to choose something else as a default? Or, is this actually a sign of some physical problem? The board looks OK... Since I've been doing more reading than programming and I'm waiting on a new joystick cap I haven't fiddled with the 7-segment displays yet.