Andrew Baldwin

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About Andrew Baldwin

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  1. Andrew Baldwin broken/gone?

    I'm still getting the same, not fixed from here
  2. Andrew Baldwin broken/gone?

    I have tried again....unfortunately the site....either from Google or from the links in the Papilio IDE are still taking me to the Incorrect Pages.....also......I'm getting VIRUS warnings from my installed Virus careful!
  3. Andrew Baldwin broken/gone?

    I'm the same, I sent an email to them yesterday to make them aware, one minute it was there the next it wasn't
  4. Andrew Baldwin

    How does data get from the PC to the Spartan-6 Flash

    @Magnus, as always thanks for taking the time to respond. Couple of further questions follow on, I'll apologise in advance, I am quite new to this 1) Is there an app note available on this technique? I can imagine its not a 'unique' application. 2) What's the purpose of the second serial interface from the FTDI device to the FPGA (MPSSE)? many thanks Andrew
  5. Andrew Baldwin

    How does data get from the PC to the Spartan-6 Flash

    @johnbeetem Thanks for I can see what is being done. My mistake, I thought all bitstreams where automatically loaded to the FLASH from the PC software, but, what you've pointed out makes perfect sense now. In normal use, the FTDI device becomes a JTAG programmer sending the configuration directly to the FPGA. Then, if you want to program the FLASH so the board can be stand-alone, there must be an option in the software that firstly JTAGs the FPGA to be the FLASH programmer, using the second serial bus generated by the FTDI device as the data stream... thanks again Andrew
  6. Hello Forum, My first time on a Forum, hope I get the etiquette correct. Recently got my Papilio Duo and a LogicStart wingy, itching to get it all running. Intend to VHDL, not drag and drop...that's the intention anyway. Essentially, being from an electronics background, I like to know what's going on. To that end, I've been wading my way through the plethora of Xilinx datasheets associated with the Spartan-6-LX9. At the moment I have couple of quick questions for the collective forumers The LX9 FPGA is set with M0 =1 and M1 =0, this sets the device in Serial Master Mode so it will get its configuration bit stream from the Flash on power up or if PROGRAM_B is pulled low, so : 1) How does data from the PC get programmed to the Flash? 2) I see other questions relating to the PC software configuring the FPGA directly through the USB port,, am I missing something in the circuit diagram, I cant see how this is possible? Unless there is something pre-configured, pre-programmed that we are shielded from....... hope they're not too stupid questions. Thanks Andrew