SergeyS.

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Posts posted by SergeyS.


  1. Also I've noticed a weird thing.

    Some background first. The device I design is the cartridge driver which should receive data via SPI from the MCU and then read and send to cartridge.

    So the weird thing is when I add the delay between data I send to the cartridge to see in the display what actually I received, it works good all the time. I receive the correct amount of data and the data itself is correct. But when I remove this delay to print data with the high speed the problem returns. I don't know how this part can influent on data read from SPI. There is an independent process which controls the cartridge, and it starts only on demand and after the SPI transaction is finished.

    Maybe there is some internal interference in the FPGA structure, I have no idea...


  2. Hello Thomas,

    I'm not sure if I allowed to send the whole design due to NDA. Though I can share required information. The SPI data rate is 500 kHz to 10 MHz (I tested in this range, and result is the same). SDRAM works with 100 MHz clock frequency. The amount of data is tens - thousands of kbits.

    The start of the SPI transaction is showed in the simulation below. You can see both SPI data and Wishbone data in it.

    image.thumb.png.72df15039ad44556249ba924bd54b199.png

    And here's the finish of the SPI transaction

    image.thumb.png.60ae535e906140aeb953b088691b2ee4.png

    Here I send 220 x 32 = 7040 bits.

    The simulation code is

    cs <= '0';
    		-------------------------------
    		
    		for i in 0 to 219 loop
    		
    			temp <= std_logic_vector(to_unsigned(i, temp'length));
    		
    			for j in 0 to 31 loop
    		
    				sck <= '1';
    				if j = 0 then
    					mosi <= '0'; 
    				else mosi <= temp(31);
    				end if;
    				wait for 10 ns;
    				
    				temp <= temp(30 downto 0) & '0';
    		
    				sck <= '0';
    				wait for 10 ns;
    				
    			end loop;	
    		
    		end loop;
    				
    		wait for 10 ns;
    			
    		cs <= '1';

    I don't know if this information is useful though...

    Kind regards,

    Sergey


  3. Hello Thomas

    Sorry for not responding for such a long time, I was working on other project, and recently returned to FPGA. I followed your recommendations and finally got the SDRAM controller worked. I used Hamster's controller with your modification and the Wishbone interface from your Bonfire project. Thank you very much for your support!

    Though now I faced another issue. My project works as follows. It receives data via SPI interface and saves it into SDRAM, then after some event occurs it reads data from RAM into array block-wise. The problem is that it works very unstable, sometimes the amount of send and received bytes doesn't match, sometimes it doesn't receive data at all. I was thinking it's the problem of my SPI driver, but I used several of them and still no effect.

    Also I was trying to simulate the code and it works perfectly all the time. I was monitoring the signals with the logic analyzer, and it also shows no problem with SPI interface, no jitter, no extra pulses. And the issue doesn't depend on the SPI data rate.

    Here's the code which implements operations with SPI and SDRAM. Maybe I do something wrong here, and don't notice it due to the lack of experience in VHDL.

    RAM_process: process (clk_100)
    		begin
    			if rising_edge (clk_100) then
    				case RAM_state is
    				-------------------waiting for command------------------------
    					when R_idle =>
    						
    						if spi_data_ready = '1' and spi_data_ready_prev = '0' then
    							wbs_dat_i <= spi_rx_buffer;
    							RAM_state <= R_write;
    							wbs_we_i <= '1';
    							wbs_stb_i <= '1';
    							wbs_cyc_i <= '1';
    							spi_receive_counter <= spi_receive_counter + 1;	
    						end if;	
    						spi_data_ready_prev <= spi_data_ready;
    					
    						if print_process = '0' then
    							read_addr <= (others => '0');
    						end if;	
    							
    						if start_read_from_RAM = '1' then 
    							RAM_state <= R_read;
    							wbs_cyc_i <= '1';
    							wbs_stb_i <= '1';
    							wbs_we_i <= '0';
    							word_counter <= (others => '0');
    						end if;
    						
    						if cs = '1' then 
    							wbs_stb_i <= '0';
    							wbs_cyc_i <= '0';
    							wbs_we_i <= '0';
    							received_row_counter <= std_logic_vector(to_unsigned(to_integer(unsigned(spi_receive_counter) / 11), received_row_counter'length));
    							RAM_state <= R_disable;
    						end if;	
    					------------------ write data to memory---------------	
    					when R_write =>
    						if wbs_ack_o = '1' then	
    							write_addr <= write_addr + 1;
    							RAM_state <= R_idle;
    						else
    							RAM_state <= R_write;
    						end if;
    					------------------ read data from memory---------------	
    					when R_read =>
    						if wbs_ack_o = '1' then
    							if word_counter = "10110" then
    								if start_read_from_RAM = '0' then 
    									wbs_cyc_i <= '0';
    									wbs_stb_i <= '0';
    									if cs = '0' then
    										RAM_state <= R_idle;
    									else
    										RAM_state <= R_disable;
    									end if;
    								end if;	
    							else 
    								print_data (to_integer(unsigned(word_counter))) <= wbs_dat_o (31 downto 16);
    								print_data (to_integer(unsigned(word_counter)) + 1) <= wbs_dat_o (15 downto 0);
    								word_counter <= word_counter + 2;
    								read_addr <= read_addr + 1;
    							end if;	
    						else
    							RAM_state <= R_read;
    						end if;
    					------------------ disabled SPI interface---------------	
    					when R_disable =>
    						
    						if cs = '0' then
    							write_addr <= (others => '0');
    							spi_receive_counter <= (others => '0');
    							RAM_state <= R_idle;
    						end if;	
    						
    						if start_read_from_RAM = '1' then 
    							RAM_state <= R_read;
    							wbs_cyc_i <= '1';
    							wbs_stb_i <= '1';
    							wbs_we_i <= '0';
    							word_counter <= (others => '0');
    						end if;
    						
    						if print_process = '0' then
    							read_addr <= (others => '0');
    						end if;	
    
    					when others =>
    						RAM_state <= R_idle;		
    				end case;
    			end if;	
    		end process;

    Could anyone please help me?...

    Kind regards,

    Sergey


  4. Hello to all,

    Thank you very much for your advises. I was trying to understand both Hamster's SDRAM controllers (simple and extended (ZPuino one)). The last one seems to be quite difficult for understanding for me so far. 

    Alvie, could you please give some hints why this huge controller is so... huge? I mean what are its advantages before the simple one? (sorry if my question seems stupid)

    I made some success with the simple SDRAM controller, though I still have some random misreads. 

    Kind regards,

    Sergey


  5. Hello,

    I'm a newbie in the FPGA, and I'm managing with the Papilio Pro Board. The problem is I can't make the SDRAM work correctly. I was trying to use the Hamster's SDRAM controller, and did as he describes, but I get weird results.

    First, sometimes it reads with random mistakes (though it might be a write problem, I don't know)

    Second, sometimes during sequential read it reads first 3-4 values the same and only then starts to increment address.

    Could you please advise some VHDL code example of how to explore the Hamster's SDRAM controller (or any other)?

    Hamsterworks wiki site doesn't work for some reason so I can't read his explanation once more...

    Kind regards,

    Sergey