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  1. Skip

    SK-Synth source?

    Thanks andY, I'll give that a try. The web site is so badly broken I couldn't find any contact info. I have read about the Tiny Synth and XFM ( projects, but neither appear to have published their RTL code, at least I couldn't find it. I recently ported Greg Taylor's clone of the OPL3 to the surplus Panologic thin clients ( and and I'm currently working on porting some of the RetroCade code. The second generation Panologic device is based on a LX150 Spartan 6 and has a 24 bit capable Wolfson codec so it should be possible to make one heck of a nice synth for it. Skip
  2. Skip

    SK-Synth source?

    I'm interested in playing with the Sk-synth core mentioned on the RetroCade home page, but the entire site seems to have been non-functional for over a year at least. It's still there, but it just throws PHP errors. Did anyone happen to checkout the code from when it was available? If so I'd love to get a copy. Skip
  3. Skip

    Papilio "Sump" Logic Analyzer

    Are there any command line tools or example code to setup advanced triggers? The only program I've found that supports the advanced trigger is a Windows executable which doesn't help me since I'm running Linux. Skip
  4. Thanks Jack !! That fixed all of my build issues. Sorry for all of the noise and confusion! I've learned a lot in the last couple of weeks. Skip
  5. Hi @Jack Gassett, I think I finally got it right. Give it a look and let me know what you think. Skip
  6. Hi @Jack Gassett, Opps... hold off on pulling the changes I just found a problem. I had replaced DesignLab-1.0.8/examples with the DesignLab_Example git repository. I just discovered that there's no example/libraries subdirectory in the release. Sorry about that! Skip
  7. Hi @Jack Gassett, I finished fixing all Benchy_Sump_LogicAnalyzer_Standalone targets and I've sent you a pull request. I've tested the DUO bit file built from a fresh tree with the changes. I haven't tested the other targets since I don't have hardware. For a while I didn't think the Papilio_One_500K target working because it appeared hang while routing, however it was just REALLY slow. I can understand if a smaller part takes more time to route than a larger part because it is fuller, but the 250K part routed MUCH faster! Any idea of what's happening here? Is this typical? Skip
  8. Hi @Jack Gassett, I fixed all of the issues with the Benchy_Sump_LogicAnalyzer_Standalone example for the DUO ONLY. I'll fix the other targets and then send you a pull request. I suspect other examples will have similar problems. I'm going to try to do some global search and replaces to fix the issues on all of the .xise files in the examples and then test a few. I would probably take days for my pokey machne to build all examples and targets! One of the biggest issues on Linux was that there was a .../examples/libraries/clocks AND a .../examples/libraries/Clocks. I moved all of the files from ../examples/libraries/clocks into ../examples/libraries/Clocks and then deleted ../examples/libraries/clocks. Any projects with references to the lower case clocks will now be broken on Linux, of course Windows won't care. Skip
  9. Hi @mkarlsson! I'm very new to this ... but I've been doing a LOT of reading of old posts, etc. I happy you are still around, most of the treads I've been reading here there and everywhere seem to have gone quiet a couple of year ago. I'm very impressed with all of the work everyone has put into OLS and related projects! I hadn't mentioned it, but I get garbage at 200 Mhz even without RLE. I get good data at 100 Mhz and 20 Mhz w/o RLE which are the only other clock rates I've tried so far. The Papilio DUO is the only hardware I have right now so I can't really tell if I have a client problem or a target problem. I'm going to try to port the Verilog implementation to my DUO and see how it compares. I tried using pulseview briefly, but it doesn't seem to recognize my Papilio. Skip
  10. @Jack Gassett, I just succeeded in rebuilding the Benchy_Sump_LogicAnalyzer_Standalone example, but I did run into some issues. Some issues were related to running on Linux (file system case sensitivity), some were related to references to "../../../DesignLab/build/windows/work/examples/", and some were related to an apparent reorganization of the tree structure. I forked DesignLab_Examples on github and committed my changes to the fork. I'm going to take a look at the RLE stuff and see if I can contribute a fix. Don't expect to much, I'm just learning VHDL. Skip
  11. Hi @Jack Gassett, After I copied ols.profile-papilio-duo.cfg from the DesignLab tree into the ols plugins directory I had some success using the ols- client from as long as I leave Run Length Encoding disabled. I guess my primary question at this point is if there is any reason I need to use the ols version bundled with DesignLab? Enabling RLE corrupts the data badly. I'm using a bus I2C bus as a test, with RLE disabled the clock is a very nice and stable 350Khz. When I enable RLE it looks completely different. Skip
  12. Hi Jack, I ran the script manually and the problem appears to be a missing dependency (missing requirement [10.0] osgi.wiring.package). A full log of the run is attached. This is a pretty virgin install of Ubuntu 16.04.1 LTS, I've installed it from scratch when I got my DUO and I've only been installing Papilio related tools on it. Skip Logic_Analyzer.log
  13. Hi @Jack Gassett, I've installed DesignLab-1.0.8 and I was able to successfully run the Papilio_DUO_QuickStart example (BTW: Way cool, no installation issues at all on Ubuntu 64 bit). When I click the logic analyzer icon the bit file is downloaded successfully, but the logic analyzer never starts. No messages are displayed after the bit file is programmed. If I say "No" to "Would you like to load a Logic Analyzer..." dialog no messages are displayed either. I had installed ols- that I downloaded from prior to installing DesignLab so I tried it and it ran (sort of). I see a 100Mhz clock on channel 1, but I can't find any configuration screens to select clocking, capture width, etc. Does the bit file loaded by DesignLab need to used with the DesignLab OLS client? This is the coolest thing I've played with in YEARS! I've already run CP/M and Pacman on the board, I can't wait to get the logic analyzer running! Skip
  14. Thanks Jack for link, I'll give it a try! Skip
  15. Hi @Jack Gassett, I've flashed the 8 channel Logic Analyzer for the Papilio DUO bit file I found in ./build/shared/tools/logicanalyzers/DUO_LX9/papilio_duo_lx9.bit successfully. I've unplugged the Papilio and plugged it back in again, but it's only enumerating as the JTAG device, I don't see the serial port. Do I assume correct that I should be plugging in the USB FPGA connector? The green LED is flashing at about a 1 Hz rate. I'm running Ubuntu 16.04.1 LTS 64 bit. lsusb shows: Skip