keesj

Members
  • Content count

    27
  • Joined

  • Last visited

  • Days Won

    1

Everything posted by keesj

  1. Hi, The code up until the last part looks quite similar to that I have done. https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/tremolo.vhd#L68 starts looking fishy. * Normally.. simply always use rising edges (and specially of the clock) * Your current process will only be "woken" up on a single bit transition(the control bit) but this will never happen unless you enable line 34 again.. https://github.com/telamon/papilio-dspwing/blob/865e322b7eb3d761216595fead3c85fb294811ed/tremolo.vhd#L68
  2. wishbone address bits

    Hi, I can see how this might be useful if you want word aligned memory access indeed. In the example I posted above only a single bit is used to discriminate so I think something else might be going on. https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/COMM_zpuino_wb_UART.vhd#L251
  3. Hi, I am having some issues understanding the wishbone addressing used. I taking the UART as example My main question is "what bit is wb_adr_i(2)" in the initial wishbone_in? https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/COMM_zpuino_wb_UART.vhd#L251 100 bits of wishbonne: wishbone_in : in std_logic_vector(100 downto 0); 25? bits of wb_address: signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) map wishbone bit 3 to??? wb_ard_1 wb_adr_i <= wishbone_in(27 downto 3); case wb_adr_i(2) is ?
  4. wishbone address bits

    Having talked with a few people about this I think the code would better be rewritten as signal wb_adr_i: std_logic_vector(23 downto 0); then case wb_adr_i(0) becomes the first bit It is possible that the bits 23 downto 19 or contain the wishbone address?
  5. Hello,I am working on a modified version of Wishbone_to_Registers does including it in my project mean anything about the license of my own code?
  6. New VHDL Library

    Hi, I have been working on my first VHDL library for the papillio. Things are starting to work but I have a few annoyances/things I do not understand: 1) When I create a new wishbone library (from VHDL) I en up with the edit_library.ino file that offers me different options like (Define your chip) e.g. sketchdir://Chip_Designer.xise Should that code be able to compile/syntax check? I always end up with ERROR: Could not find symbol "mylib_wb" or similar when I press the green arrow 2) When I edit the target specific files e.g. sketchdir://circuit/PSL_Papilio_Pro_LX9.xise for example I alway have to "re-add" my vhdl files into the DesignLab library. How do I fix this issue?
  7. data_valid pattern?

    FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version (chaper 7.2.4) talks about Interface circuits and using one of the following methods A flag FF (Flip Flop) A flag FF and a one word buffer A Fifo buffer To solve this problem
  8. data_valid pattern?

    Hello, I am starting on my first real project and trying to find a good example of signaling. Many examples I see create a component that does something similar to what is listed bellow in clk in data[8] in data_valid process (clk) state machine when idle => if data_valid change state to blabla when blabla => do stuff Basically a "data_valid" or similar is used to start the process. I am wondering how it normally is prevented that the state machine is not run multiple times(if the signal does not change) https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/tx_unit.vhd#L54 or https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/spi.vhd#L45 and https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/sid_filters.vhd#L22 It there a way to enforce the "data_valid" signal to be low before we start the next iteration or is this somehow not necessary and I am missing something ?
  9. Hi, I stumbled up on this (ratter long but interesting video on "icesoc" ) I might give us some ideas
  10. Hi, I am based in the Netherlands and want to order a few parts (Papilio pro, some wings and io buffers). What is the best plat to order the items? When I order from the US I normally have to pay additional handling fees and I would like to avoid this I don't mind waiting a few day before getting the stuff I have seen a few places that offer the hardware (sparkfun, seedstudio,this website) can anybody recommend where to get the hardware?
  11. SPI MODE0

    Hi, I am trying to interface with an 8x8 Led-Digit driver. I Started by bit banging the code to get something working void send(int value) { // enable CS digitalWrite(MX_CS, LOW); w(); int v = value; for (signed int x = 15; x >= 0; x--) { digitalWrite(MX_DATA, ((v >> x) & 0x1) ? 1 : 0); w(); digitalWrite(MX_CLK, HIGH); w(); digitalWrite(MX_CLK, LOW); w(); } digitalWrite(MX_CS, HIGH); w(); } Next I moved to using the zpuino SPI block. I looked at the datasheet above and the wikipedia article on SPI and determined I need to send my SPI message using "MODE0". When I do so the SPI device is not working properly And from looking at the SPI implementation I think the problem is that the values are always set on the rising edge of the clock while for MODE0 the value should be set before (e.g. on the falling edge). Am I missing something? (from experimenting using MODE2 apprears to work but then clock stays high in between cycles) Here is my setup (for the fun o it): I hoped to be able to use a pin of the IO BufferWing to be able to drive the display but this did not work.
  12. Hi, What for for me currently is to open a project e.g. ZPUino multiple serial ports and add the component (e.g. spi) and start modifying it but I am not 100% sure this is the right way to create a clean library
  13. Hi, I am trying to modify the standard Wishbone peripherals. Here is what I did I cloned the git repository containing the DesignLab examples, renamed my local libraries to libraries-old and configured the ide to use DesignLab_Examples as Sketchdir.(it llook like the examples directory might also need a rename) Next using the file open I go to libraries/ZPUino_Wishbone_Peripherals and open the "edit_library.ino" in that folder. Next I clicked on the sketchdir://Chip_Designer.xise to open the ISE. This opens the ISE editor. For this example the editor open with an error that it can not find AUDIO_zpuino_wb_pokey.vhd So I started seaching for that file and found it in a different folder where I found a similar project For short DesignLab_Examples/00.Papilio_Schematic_Library/Libraries/Wishbone_Peripherals and DesignLab_Examples/libraries/ZPUino_Wishbone_Peripherals Are similar but different. The Wishbone_Peripherals is lacking a project file and the ZPUino_Wishbone_Peripherals is lacking a vhd file. How am i supposed to modify the library?
  14. Papilio Pro still produced?

    Currently you can get them for cheap at seeed studio: https://www.seeedstudio.com/Papilio-Pro-p-1301.html
  15. SPI MODE0

    Hi, I started looking into the code to try and understand the problem myself. the SPI master does have enough flags passed to the code e.g. spi_samprise is kinda taken into account to determine when to sample the signal (at rise or fall of the clock) https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/COMM_zpuino_wb_SPI.vhd#L250 and (I think sets the do_sample correctly) https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/spi.vhd#L81 However https://github.com/GadgetFactory/DesignLab_Examples/blob/master/libraries/ZPUino_Wishbone_Peripherals/spi.vhd#L95 Will alway shift on the rising edge of the spi clock. I made small modifications trying to fix it but I am getting into trouble because I need to skip the first rising edge e.g. if try to I skip the first rising edge all my data if off by one clock cycle.
  16. Hi, Yesterday I started playing with the sump logic analyzer code on the Papilio Pro. I took the basic example and started modifying the system to add an additional serial port and started sniffing that serial port. In my sketch I added some serial.write and everything works as expected until I start writing 4 bytes to the serial e.g not "kee" but "kees". At that point OLS no longer works. any hints what is going on? In the attached picture you can see that the serial.write actually takes some time from the CPU to execute is this blocking the wishbone bus or something similar causing the Logic analyzer to stop working? I am using ols-0.9.7.2. My goal is to be able to "trigger" on a certain UART character or other events on the system. I plan on glueing the SUMP with the UART or other blocks. Is the current code in the IDE the best one to follow or should I base the code on the new whishbone based interface?. I have had more little problems: In OLS I can not configure the system to use 1 bank e.g. 8 bits as the SUMP code currently always sends 16 bits/2 bytes I would be interested in accessing the SUMP data over a different port from the UART (possibly JTAG or a different port) but the jtagserver is not ported to linux It looks like RLE is not working (kinda documented but not very clear what the status is)
  17. Well the behavior is that the capture never completes. One small modification I did that appeared to improve a little was replacing the if(serial.available) by while(serial.available). I will perform more tests(also try @bnusbick's suggestion.
  18. Yea it looks like there is no place to order the Papilio pro from the EU(out of stock)
  19. Hi, I am sure is it documented somewhere but what is the best way to modify existing library items? I am currently making the modifications in opt/DesignLab-1.0.8/libraries but this tends to break my other designs.
  20. Modifying the libraries

    That sounds like a good plan
  21. CaseSensitive bit

    Hello, I am using DesignLab 1.0.8 under Linux and I have a small problem when generating new bit files. The problem is that the case of the files is different from the default and therefore the IDE won't flash my new file. I either need to rename the file or create a symlink. For example the Multiple_Serial_Ports example Creates a Papilio_Pro.bit file while the IDE expects papilio_pro.bit. With kind regards
  22. Hi, I tried registering to the forum with a new (work) account but this currently fails. I am not getting the confirmation email.
  23. Hi, The same applies to ubuntu 16.10.I suggest upgrading to ols-0.9.7.2 (for java 1.8 support)
  24. ZPUino HDL Source Code

    The zip as posted (sha556 fe10bd54b6f01939d68df776484383f647c00987aad256aa9a5fe77b1d5caa05 ../../ZPUino-HDL-Source-V1.0.zip) files does currently not extract properly under Linux keesj@700z:~/Downloads/tmp/zp$ unzip ../../ZPUino-HDL-Source-V1.0.zip Archive: ../../ZPUino-HDL-Source-V1.0.zip 971a1459607f23e6b9814e444df8716ee877de98 extracting: ZPUino-HDL-Source-V1.0 checkdir error: ZPUino-HDL-Source-V1.0 exists but is not directory unable to process ZPUino-HDL-Source-V1.0/.gitignore. checkdir error: ZPUino-HDL-Source-V1.0 exists but is not directory unable to process ZPUino-HDL-Source-V1.0/.project. checkdir error: ZPUino-HDL-Source-V1.0 exists but is not directory unable to process ZPUino-HDL-Source-V1.0/Papilio/. checkdir error: ZPUino-HDL-Source-V1.0 exists but is not directory .. .. checkdir error: ZPUino-HDL-Source-V1.0 exists but is not directory unable to process ZPUino-HDL-Source-V1.0/zpu/sw/startup/time.c. I found a workaround for the first problem by adding the path to be extrated but still there are some errors unzip ../../ZPUino-HDL-Source-V1.0.zip ZPUino-HDL-Source-V1.0/* keesj@700z:~/Downloads/tmp/zp$ unzip ../../ZPUino-HDL-Source-V1.0.zip ZPUino-HDL-Source-V1.0/* Archive: ../../ZPUino-HDL-Source-V1.0.zip 971a1459607f23e6b9814e444df8716ee877de98 inflating: ZPUino-HDL-Source-V1.0/.gitignore inflating: ZPUino-HDL-Source-V1.0/.project creating: ZPUino-HDL-Source-V1.0/Papilio/ creating: ZPUino-HDL-Source-V1.0/Papilio/papilio_one_250k_vanilla_ise/ inflating: ZPUino-HDL-Source-V1.0/Papilio/papilio_one_250k_vanilla_ise/papilio_one_250k_vanilla_ise.xise creating: ZPUino-HDL-Source-V1.0/Papilio/papilio_one_500k_vanilla_ise/ inflating: ZPUino-HDL-Source-V1.0/Papilio/papilio_one_500k_vanilla_ise/papilio_one_500k_vanilla_ise.xise creating: ZPUino-HDL-Source-V1.0/Papilio/papilio_pro_lx9_vanilla_ise/ inflating: ZPUino-HDL-Source-V1.0/Papilio/papilio_pro_lx9_vanilla_ise/papilio_pro_lx9_vanilla_ise.xise inflating: ZPUino-HDL-Source-V1.0/zpu/hdl/zpuino/bootloader/bootloader.hex .. file #621 (ZPUino-HDL-Source-V1.0/zpu/hdl/zpuino/bootloader/crt0.S): mismatch between local and central GPF bit 11 ("UTF-8"), continuing with central flag (IsUTF8 = 1) file #662 (ZPUino-HDL-Source-V1.0/zpu/hdl/zpuino/contrib/zpuino_pokey.vhd): mismatch between local and central GPF bit 11 ("UTF-8"), continuing with central flag (IsUTF8 = 1) Perhaps somebody can gide me to a github version of the code? The original author also added some new cool stuff in the 2.0 version https://github.com/alvieboy/ZPUino-HDL