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Everything posted by keesj

  1. Hi, Is it possible to control the COL-A and COL-C? The schematics for the Logic Megawing is not clear on this (and the ucf does not contain this information either)
  2. keesj

    can wishbone library

    Hi, Over the last couple of months I have been working on a module to communicate over the can bus. I have been using the papilio pro board as main development platform for that purpose. As a result I created a wishbone interface and some code running on the zpuino to be able to interface with the can bus. Using DesignLab was a very nice way to get started. thank you for that. the project can be found here and documentation here
  3. keesj

    Is gadget factory moving sites or shutting down?

    Hello, Good to know. there are some other pages that currently down (see other topic)
  4. keesj

    Is gadget factory moving sites or shutting down?

    Hi, I do not know what is going on. I can also not download the IDE.
  5. Hi, Can you give a bit more details? on what you mean with 0-10V ADC. Are you talking about an analog signal (if so how fat does it change)? it is input or output from the DUO's perspective?
  6. keesj

    New (potential) user

    Hi, I found the following videos quite inspiring
  7. Hi, The code up until the last part looks quite similar to that I have done. starts looking fishy. * Normally.. simply always use rising edges (and specially of the clock) * Your current process will only be "woken" up on a single bit transition(the control bit) but this will never happen unless you enable line 34 again..
  8. keesj

    wishbone address bits

    Hi, I can see how this might be useful if you want word aligned memory access indeed. In the example I posted above only a single bit is used to discriminate so I think something else might be going on.
  9. Hi, I am having some issues understanding the wishbone addressing used. I taking the UART as example My main question is "what bit is wb_adr_i(2)" in the initial wishbone_in? 100 bits of wishbonne: wishbone_in : in std_logic_vector(100 downto 0); 25? bits of wb_address: signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) map wishbone bit 3 to??? wb_ard_1 wb_adr_i <= wishbone_in(27 downto 3); case wb_adr_i(2) is ?
  10. keesj

    wishbone address bits

    Having talked with a few people about this I think the code would better be rewritten as signal wb_adr_i: std_logic_vector(23 downto 0); then case wb_adr_i(0) becomes the first bit It is possible that the bits 23 downto 19 or contain the wishbone address?
  11. Hello,I am working on a modified version of Wishbone_to_Registers does including it in my project mean anything about the license of my own code?
  12. keesj

    New VHDL Library

    Hi, I have been working on my first VHDL library for the papillio. Things are starting to work but I have a few annoyances/things I do not understand: 1) When I create a new wishbone library (from VHDL) I en up with the edit_library.ino file that offers me different options like (Define your chip) e.g. sketchdir://Chip_Designer.xise Should that code be able to compile/syntax check? I always end up with ERROR: Could not find symbol "mylib_wb" or similar when I press the green arrow 2) When I edit the target specific files e.g. sketchdir://circuit/PSL_Papilio_Pro_LX9.xise for example I alway have to "re-add" my vhdl files into the DesignLab library. How do I fix this issue?
  13. keesj

    data_valid pattern?

    FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version (chaper 7.2.4) talks about Interface circuits and using one of the following methods A flag FF (Flip Flop) A flag FF and a one word buffer A Fifo buffer To solve this problem
  14. keesj

    data_valid pattern?

    Hello, I am starting on my first real project and trying to find a good example of signaling. Many examples I see create a component that does something similar to what is listed bellow in clk in data[8] in data_valid process (clk) state machine when idle => if data_valid change state to blabla when blabla => do stuff Basically a "data_valid" or similar is used to start the process. I am wondering how it normally is prevented that the state machine is not run multiple times(if the signal does not change) or and It there a way to enforce the "data_valid" signal to be low before we start the next iteration or is this somehow not necessary and I am missing something ?
  15. Hi, I stumbled up on this (ratter long but interesting video on "icesoc" ) I might give us some ideas
  16. Hi, I am based in the Netherlands and want to order a few parts (Papilio pro, some wings and io buffers). What is the best plat to order the items? When I order from the US I normally have to pay additional handling fees and I would like to avoid this I don't mind waiting a few day before getting the stuff I have seen a few places that offer the hardware (sparkfun, seedstudio,this website) can anybody recommend where to get the hardware?
  17. keesj


    Hi, I am trying to interface with an 8x8 Led-Digit driver. I Started by bit banging the code to get something working void send(int value) { // enable CS digitalWrite(MX_CS, LOW); w(); int v = value; for (signed int x = 15; x >= 0; x--) { digitalWrite(MX_DATA, ((v >> x) & 0x1) ? 1 : 0); w(); digitalWrite(MX_CLK, HIGH); w(); digitalWrite(MX_CLK, LOW); w(); } digitalWrite(MX_CS, HIGH); w(); } Next I moved to using the zpuino SPI block. I looked at the datasheet above and the wikipedia article on SPI and determined I need to send my SPI message using "MODE0". When I do so the SPI device is not working properly And from looking at the SPI implementation I think the problem is that the values are always set on the rising edge of the clock while for MODE0 the value should be set before (e.g. on the falling edge). Am I missing something? (from experimenting using MODE2 apprears to work but then clock stays high in between cycles) Here is my setup (for the fun o it): I hoped to be able to use a pin of the IO BufferWing to be able to drive the display but this did not work.
  18. Hi, What for for me currently is to open a project e.g. ZPUino multiple serial ports and add the component (e.g. spi) and start modifying it but I am not 100% sure this is the right way to create a clean library
  19. Hi, I am trying to modify the standard Wishbone peripherals. Here is what I did I cloned the git repository containing the DesignLab examples, renamed my local libraries to libraries-old and configured the ide to use DesignLab_Examples as Sketchdir.(it llook like the examples directory might also need a rename) Next using the file open I go to libraries/ZPUino_Wishbone_Peripherals and open the "edit_library.ino" in that folder. Next I clicked on the sketchdir://Chip_Designer.xise to open the ISE. This opens the ISE editor. For this example the editor open with an error that it can not find AUDIO_zpuino_wb_pokey.vhd So I started seaching for that file and found it in a different folder where I found a similar project For short DesignLab_Examples/00.Papilio_Schematic_Library/Libraries/Wishbone_Peripherals and DesignLab_Examples/libraries/ZPUino_Wishbone_Peripherals Are similar but different. The Wishbone_Peripherals is lacking a project file and the ZPUino_Wishbone_Peripherals is lacking a vhd file. How am i supposed to modify the library?
  20. keesj

    Papilio Pro still produced?

    Currently you can get them for cheap at seeed studio:
  21. keesj


    Hi, I started looking into the code to try and understand the problem myself. the SPI master does have enough flags passed to the code e.g. spi_samprise is kinda taken into account to determine when to sample the signal (at rise or fall of the clock) and (I think sets the do_sample correctly) However Will alway shift on the rising edge of the spi clock. I made small modifications trying to fix it but I am getting into trouble because I need to skip the first rising edge e.g. if try to I skip the first rising edge all my data if off by one clock cycle.
  22. Well the behavior is that the capture never completes. One small modification I did that appeared to improve a little was replacing the if(serial.available) by while(serial.available). I will perform more tests(also try @bnusbick's suggestion.
  23. Hi, Yesterday I started playing with the sump logic analyzer code on the Papilio Pro. I took the basic example and started modifying the system to add an additional serial port and started sniffing that serial port. In my sketch I added some serial.write and everything works as expected until I start writing 4 bytes to the serial e.g not "kee" but "kees". At that point OLS no longer works. any hints what is going on? In the attached picture you can see that the serial.write actually takes some time from the CPU to execute is this blocking the wishbone bus or something similar causing the Logic analyzer to stop working? I am using ols- My goal is to be able to "trigger" on a certain UART character or other events on the system. I plan on glueing the SUMP with the UART or other blocks. Is the current code in the IDE the best one to follow or should I base the code on the new whishbone based interface?. I have had more little problems: In OLS I can not configure the system to use 1 bank e.g. 8 bits as the SUMP code currently always sends 16 bits/2 bytes I would be interested in accessing the SUMP data over a different port from the UART (possibly JTAG or a different port) but the jtagserver is not ported to linux It looks like RLE is not working (kinda documented but not very clear what the status is)
  24. Yea it looks like there is no place to order the Papilio pro from the EU(out of stock)