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keesj last won the day on October 12 2017

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About keesj

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  1. Hi, Is it possible to control the COL-A and COL-C? The schematics for the Logic Megawing is not clear on this (and the ucf does not contain this information either)
  2. keesj

    can wishbone library

    Hi, Over the last couple of months I have been working on a module to communicate over the can bus. I have been using the papilio pro board as main development platform for that purpose. As a result I created a wishbone interface and some code running on the zpuino to be able to interface with the can bus. Using DesignLab was a very nice way to get started. thank you for that. the project can be found here and documentation here
  3. keesj

    Is gadget factory moving sites or shutting down?

    Hello, Good to know. there are some other pages that currently down (see other topic)
  4. keesj

    Is gadget factory moving sites or shutting down?

    Hi, I do not know what is going on. I can also not download the IDE.
  5. Hi, Can you give a bit more details? on what you mean with 0-10V ADC. Are you talking about an analog signal (if so how fat does it change)? it is input or output from the DUO's perspective?
  6. keesj

    New (potential) user

    Hi, I found the following videos quite inspiring
  7. Hi, The code up until the last part looks quite similar to that I have done. starts looking fishy. * Normally.. simply always use rising edges (and specially of the clock) * Your current process will only be "woken" up on a single bit transition(the control bit) but this will never happen unless you enable line 34 again..
  8. keesj

    wishbone address bits

    Hi, I can see how this might be useful if you want word aligned memory access indeed. In the example I posted above only a single bit is used to discriminate so I think something else might be going on.
  9. keesj

    wishbone address bits

    Having talked with a few people about this I think the code would better be rewritten as signal wb_adr_i: std_logic_vector(23 downto 0); then case wb_adr_i(0) becomes the first bit It is possible that the bits 23 downto 19 or contain the wishbone address?
  10. Hi, I am having some issues understanding the wishbone addressing used. I taking the UART as example My main question is "what bit is wb_adr_i(2)" in the initial wishbone_in? 100 bits of wishbonne: wishbone_in : in std_logic_vector(100 downto 0); 25? bits of wb_address: signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) map wishbone bit 3 to??? wb_ard_1 wb_adr_i <= wishbone_in(27 downto 3); case wb_adr_i(2) is ?
  11. Hello,I am working on a modified version of Wishbone_to_Registers does including it in my project mean anything about the license of my own code?
  12. keesj

    New VHDL Library

    Hi, I have been working on my first VHDL library for the papillio. Things are starting to work but I have a few annoyances/things I do not understand: 1) When I create a new wishbone library (from VHDL) I en up with the edit_library.ino file that offers me different options like (Define your chip) e.g. sketchdir://Chip_Designer.xise Should that code be able to compile/syntax check? I always end up with ERROR: Could not find symbol "mylib_wb" or similar when I press the green arrow 2) When I edit the target specific files e.g. sketchdir://circuit/PSL_Papilio_Pro_LX9.xise for example I alway have to "re-add" my vhdl files into the DesignLab library. How do I fix this issue?
  13. keesj

    data_valid pattern?

    FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version (chaper 7.2.4) talks about Interface circuits and using one of the following methods A flag FF (Flip Flop) A flag FF and a one word buffer A Fifo buffer To solve this problem
  14. keesj

    data_valid pattern?

    Hello, I am starting on my first real project and trying to find a good example of signaling. Many examples I see create a component that does something similar to what is listed bellow in clk in data[8] in data_valid process (clk) state machine when idle => if data_valid change state to blabla when blabla => do stuff Basically a "data_valid" or similar is used to start the process. I am wondering how it normally is prevented that the state machine is not run multiple times(if the signal does not change) or and It there a way to enforce the "data_valid" signal to be low before we start the next iteration or is this somehow not necessary and I am missing something ?