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About keesj

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  1. Is gadget factory moving sites or shutting down?

    Hi, I do not know what is going on. I can also not download the IDE.
  2. Hi, Can you give a bit more details? on what you mean with 0-10V ADC. Are you talking about an analog signal (if so how fat does it change)? it is input or output from the DUO's perspective?
  3. New (potential) user

    Hi, I found the following videos quite inspiring
  4. Hi, The code up until the last part looks quite similar to that I have done. starts looking fishy. * Normally.. simply always use rising edges (and specially of the clock) * Your current process will only be "woken" up on a single bit transition(the control bit) but this will never happen unless you enable line 34 again..
  5. wishbone address bits

    Hi, I can see how this might be useful if you want word aligned memory access indeed. In the example I posted above only a single bit is used to discriminate so I think something else might be going on.
  6. wishbone address bits

    Having talked with a few people about this I think the code would better be rewritten as signal wb_adr_i: std_logic_vector(23 downto 0); then case wb_adr_i(0) becomes the first bit It is possible that the bits 23 downto 19 or contain the wishbone address?
  7. Hi, I am having some issues understanding the wishbone addressing used. I taking the UART as example My main question is "what bit is wb_adr_i(2)" in the initial wishbone_in? 100 bits of wishbonne: wishbone_in : in std_logic_vector(100 downto 0); 25? bits of wb_address: signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits) map wishbone bit 3 to??? wb_ard_1 wb_adr_i <= wishbone_in(27 downto 3); case wb_adr_i(2) is ?
  8. Hello,I am working on a modified version of Wishbone_to_Registers does including it in my project mean anything about the license of my own code?
  9. New VHDL Library

    Hi, I have been working on my first VHDL library for the papillio. Things are starting to work but I have a few annoyances/things I do not understand: 1) When I create a new wishbone library (from VHDL) I en up with the edit_library.ino file that offers me different options like (Define your chip) e.g. sketchdir://Chip_Designer.xise Should that code be able to compile/syntax check? I always end up with ERROR: Could not find symbol "mylib_wb" or similar when I press the green arrow 2) When I edit the target specific files e.g. sketchdir://circuit/PSL_Papilio_Pro_LX9.xise for example I alway have to "re-add" my vhdl files into the DesignLab library. How do I fix this issue?
  10. data_valid pattern?

    FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version (chaper 7.2.4) talks about Interface circuits and using one of the following methods A flag FF (Flip Flop) A flag FF and a one word buffer A Fifo buffer To solve this problem
  11. data_valid pattern?

    Hello, I am starting on my first real project and trying to find a good example of signaling. Many examples I see create a component that does something similar to what is listed bellow in clk in data[8] in data_valid process (clk) state machine when idle => if data_valid change state to blabla when blabla => do stuff Basically a "data_valid" or similar is used to start the process. I am wondering how it normally is prevented that the state machine is not run multiple times(if the signal does not change) or and It there a way to enforce the "data_valid" signal to be low before we start the next iteration or is this somehow not necessary and I am missing something ?
  12. Hi, I stumbled up on this (ratter long but interesting video on "icesoc" ) I might give us some ideas
  13. Hi, What for for me currently is to open a project e.g. ZPUino multiple serial ports and add the component (e.g. spi) and start modifying it but I am not 100% sure this is the right way to create a clean library
  14. Papilio Pro still produced?

    Currently you can get them for cheap at seeed studio: