Larry McGovern

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About Larry McGovern

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  1. Fractal project with Papilio Duo

    You got it together, that's terrific!! Photos? Yes, I had exactly the same problem. There are some corrupt pixels at the maximum zoom level, which disappear after pressing the refresh button a few times. I didn't see that issue at any other zoom level. And yes, the timing report did show there was a path that didn't meet 200 MHz timing, which I bet is the cause of the issue. I did spend a little time trying to hunt that one down, but eventually moved on because i was already pretty happy with the result. If you happen to find a fix for the issue, please let me know.
  2. Fractal project with Papilio Duo

    Hi Dave, I'm glad you found the source code on github! It's been more than a year since I put this together, so I had to dust off the old files. You are correct, you will need to use the Core Generator to create the FIFO and clock manager. I used a standard FIFO with 28b x 1024 depth. I also used the clocking wizard to create 200 MHz and 100 MHz clocks from the 32 MHz input. But if you look inside MandlebrotTop.vhd, you'll see that the 100 MHz output from clk_mgr does not get used. Instead, I set both clk_200 and clk_m to the 200 MHz clock. The 100 MHz is a holdover from a previous iteration of my code, and certainly could have been cleaned up. Let me know if you get this working, and if you spot any improvements. This was one of my first VHDL projects, so I'm sure the code is less than perfect.
  3. Logic Analyzer bug on Papilio One?

    Fantastic! That bit file works perfectly with the client software. Thank you!
  4. Logic Analyzer bug on Papilio One?

    And missed your question about the Duo earlier. Yes, I have verified it in the past, but not with this exact test. I was using the logic analyzer with it a month or two ago, with no problems. I have it wrapped up in another project at the moment, but could pull it out if there is anything you want me to try on it.
  5. Logic Analyzer bug on Papilio One?

    Hi Jack, no dice The 250k bit file has exactly the same behavior on channels 16-31. I could not get channels 0-15 to work at all. I went back to the bit file that comes with DesignLab 1.0.7. (By the way, I did try the 500k file as well, but couldn't collect any data with that one.) Incidentally, my "test" was super simple. I just loaded the following sketch to an arduino board, and connected pin Tx and GND to the Papilio. Just in case you wished to replicate these results. void setup() { Serial.begin(115200); } void loop() { Serial.println("The quick brown fox jumped over the lazy dog"); delay(30); }
  6. Logic Analyzer bug on Papilio One?

    The chip says 250K, and I selected the 250K version in designlab. I've repeated these steps several times to rule out human error.
  7. I just uploaded a snap together case for the Papilio One Logic Analyzer over at Thingiverse: Enjoy!
  8. Logic Analyzer bug on Papilio One?

    I'm seeing some strange behavior with the Papilio One Logic Analyzer any time I select a sample size greater than 6 kB. It is easiest to demonstrate with an example. I have a test signal coming in on Pin 0. I am writing the sentence "The quick brown fox jumped over the lazy dog" over a serial port at 115200 baud, and repeating the sentence every 30 msec. The sentence itself takes 4 msec to write. The first image below shows a 1 MHz, 6 kB capture enabling channel group 0. This should cover 6 msec of data, and that is what I see on the logic analyzer. The UART analyzer shows the correct sentence coming across. The second image shows a 50 kHz capture, with 120 msec of data. This shows the sentence is repeated every 30 msec. The third image shows a 2 MHz, 12 kB capture enabling channel group 0. It should look exactly the same as the first image, but it doesn't. Instead, it shows a 1.5 msec word, 1.5 msec gap, and another 1.5 msec word. The two words read "er the lazy dog er the lazy dog". The fourth image shows a 5 MHz, 24 kB capture. Again, it should look like image 1 but it doesn't. Instead, we see the last 0.75 msec of the sentence, repeated 4 times. It essentially says "** dog" four times, where ** are garbage characters. That was all with only channel group 1 enabled. When I enable all four channel groups, and do a 1 MHz, 6 kB capture, I am told I will only receive 1.5 msec of data, but instead I receive 6 msec of data! When I try to capture 12 kB or 24 kB of data, it complains "Sample count too large for chosen channel groups!" So... Is this a known bug, or something new? I installed the bitfile using the "OLS" button on DesignLab 1.0.7. I have been extra careful to ensure I have selected the Papilio One 250K on both DesignLab and OLS. I've even uninstalled and reinstalled DesignLab. I also have a Papilio Duo, and the logic analyzer works for me with that board. Any ideas? Anything I should try?
  9. Fractal project with Papilio Duo

    Thanks Jack! I see the repost.
  10. Fractal project with Papilio Duo

    Hi Jack, I noticed that you put this project on your blog back in mid-July. Thanks for creating it on my behalf! If possible, could you replace the picture with an image and link to my YouTube video? Link: The current picture there is not from my project, and I would hate for the author of that picture to think that I had taken credit for their work! Also, I am certainly happy to share my VHDL code, though I’m not sure it’s best to learn VHDL from me, clearly a novice. I approached this project as a learning opportunity, and my best recommendation is for others to do the same and create as much from scratch as they can. I can certainly provide a link to the source code if you think it would enhance the blog entry. Again, thanks for putting that up there. Also (on a different topic altogether), looking forward to the Papillio Nano. I'll definitely be ordering one of those when they are ready.
  11. Fractal project with Papilio Duo

    Hi Jack, thanks for your enthusiasm! At my household, the reactions ranged from bafflement on why I had wasted so many hours doing this to "you need to get a real hobby"! LOL! Actually, my 11 year old enjoyed finding all sorts of crazy fractal patterns. She keeps coming back to this little gadget for more. It is strangely addictive, and one can get lost for long stretches of time exploring the Mandelbrot set. I just posted the SketchUp and STL files on Thingiverse with a few instructions, in case anyone is interested: Although my application was very specific, it is pretty easy to modify if someone wanted to have a different placement for the joystick and buttons. I could see rotating the screen 90 deg, moving the joystick, and setting this up as an arcade. It is a very simple design, and I'm sure someone who designed consumer products for a living would find plenty wrong with it. I'm not really interested in mass producing these, but might be persuaded to print off one or two for a few interested folks for the price of the filament (a few dollars) and shipping. (Or if you're interested, maybe in exchange for a discount on one of your new Nanos when it is ready. I'll definitely need to pick up one of those!) And I notice that Thingiverse has a new "Order this printed" button, convenient for those without access to their own 3D printer.
  12. Fractal project with Papilio Duo

    Thanks Jack! It would be an honor to see this on the Gadget Factory blog. This project was quite suitable for the Duo, since it makes use of the AVR chip for some of the basic math and input controls processing, and leaves the hard stuff to the FPGA. Also, hats off to Hamster, whose own Mandelbrot project were the inspiration for this. My project was not a copy of his (after all, my objective here was to learn), but I did learn quite a bit from his implementation on how to pipeline a project like this. I posted a few other details on the project on the YouTube post, but I suspect some of the readers here would be more interested. Here is the bullet point description: • The Atmega32U4 is used to process the analog joystick, buttons, and rotary encoder to set the cursor position, zoom, and color map. This information is sent over to the FPGA via an SPI interface. • The FPGA runs the 800x600 pixel fractal calculations at 200 MHz using the onboard DSP48s. • The fractals are saved to SRAM, with each pixel stored as a 1 byte word. • A set of selectable 12-bit color maps are stored using the FPGA BRAM. I currently have over a dozen, and am planning on adding more color maps. • An 800x600 pixel SVGA controller on the FPGA is used to send a 12-bit color image to the LCD. I used the snap-off VGA wing from the LogicStart Shield. The LCD was an inexpensive 7” screen purchased off eBay, typically used for Raspberry Pi projects. • The case for this design was 3D printed, and custom designed just for this project. Finally, the 3D case could be easily modified for a more general purpose Papilio Arcade. The Papilio Duo drops right into it. Perhaps I'll post the SketchUp file on Thingiverse if there is interest.
  13. Fractal project with Papilio Duo

    Thought I would share what I've been up to with your board. This has been a really enjoyable way to learn VHDL. This was inspired by a similar project by Hamster.
  14. Terrific product!

    Thanks Jack. Your answer makes a lot of sense. I've worked professionally with FPGA and ASIC engineers for years, but never really explored how they do their job until now. There's nothing like digging in and doing it yourself to figure out how stuff works. There is plenty here to keep me busy for a while. Though I may need to pick up another board in the not too distant future!
  15. Terrific product!

    Alvie, I'm looking forward to that blog post. In looking over the Spartan documentation, I noticed that Xilinx also has its own soft processor IP called "MicroBlaze", so clearly these are important in the world of FPGAs. I am curious how frequently a typical FPGA engineer will include one in his/her design. Always? Occasionally? It certainly seems useful if one can afford the resources. Jaxartes, I agree that creating an SPI interface from scratch to communicate with the AVR looks like a useful learning opportunity. I'm already digging into more of the many features included in the Duo and seeing plenty of potential.