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About anirbax

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  1. Hi, Is it possible to access the SPI flash on the Papillio One board from my Verilog code? Some part of the flash is taken by the bitfile for loading FPGA configuration, and I'd like to use some free flash blocks (a few hundred bytes) My RTL receives data from a UART interface, processes it (SHA-1) and needs to store the signature on non-volatile storage. If not, I will have to get a separate SPI flash chip for storage. Thanks Anirban
  2. Programming to FPGA SPI Flash not working

    Hi adamada, After programming the SPI flash, you need to power cycle (remove power and then connect power back again). Took me some time to figure out :-) --Anirban
  3. ISE Placement Error

    I see, that makes sense. Thanks, Thomas. --Anirban
  4. ISE Placement Error

    Hi, I am trying out the newbie example here: (plan to load design onto a Papilio One 250) Running synthesis gives this error: Starting Placer Phase 1.1 ERROR:Place:311 - The IOB clk is locked to site IPAD21 in bank 0. This violates the SelectIO banking rules. Other incompatible IOBs may be locked to the same bank, or this IOB may be illegally locked to a Vref site. ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed. The constraint file (downloaded from here) NET clk LOC="P89" | IOSTANDARD=LVCMOS25 | PERIOD=31.25ns; When I change the IO type to IOSTANDARD=LVCMOS33, PnR completes without error. What could be the reason why 2.5V CMOS is not supported? Thanks Anirban