DrTrigon

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  1. DrTrigon

    login / sign in issues

    Sorry I mixed up GadgetBox with Gadget Factory thus this post is on a wrong discussion board, I moved it to the correct one:
  2. DrTrigon

    Forum login / sign in issues

    Hello I have really weird login issues for days now. Basically I cannot login to this forum and my account. Whenever I logout I have to reset my password in order to be able to login again. I even tried copy-n-paste my password from a text-editor, does not work either. I have thus to assume that my password does not get stored properly, may be it's a coding issue - honestly I have no clue... I need help here!! Thanks and Greetings
  3. Dockerfile including DesignLab: https://github.com/drtrigon/docker-papilio-environment-ise/blob/master/Dockerfile.DesignLab Build it using: docker build -f Dockerfile.DesignLab -t test:latest . Run it using: docker run -e DISPLAY=$DISPLAY -v /tmp/.X11-unix:/tmp/.X11-unix -v $(pwd):/workspace test:latest bash -c "/opt/Xilinx/14.7/ISE_DS/common/bin/lin64/xlcm; DesignLab-1.0.8/DesignLab;"
  4. In order to provide your license file the License Configuration Manager (xlcm) has to be run. To make this work the package libqt4-network and a symlink are needed. I created a docker image providing these modifications. This enables to run ISE with correct license. To run ISE you need to have Docker installed and working first, then: xhost local:root docker run -e DISPLAY=$DISPLAY -v /tmp/.X11-unix:/tmp/.X11-unix -v $(pwd):/workspace drtrigon/papilio-environment-ise bash -c "/opt/Xilinx/14.7/ISE_DS/common/bin/lin64/xlcm; ise;" This will first start the License Configuration Manager allowing you to add your Xilinx.lic license file (load it from /workspace directory). After you close that dialog it finally starts ISE in a window. Further info can be found in: https://github.com/drtrigon/docker-papilio-environment-ise or https://hub.docker.com/r/drtrigon/papilio-environment-ise/ Hope that helps someone else too. Incredible to me is the fact that the whole build environment suits into a 2 GB docker image (5.88GB on the local machine) while the download of ISE is around 6 GB and the installations needs something around 20 GB. That's very cool IMHO! Thanks Jack for starting this! What are your future plans for this docker environment?
  5. Ok, I figured out how to run ISE from this docker image (tested on ubuntu 14.04): Install docker: wget -qO- https://get.docker.com/ | sh Set user and group permissions (might need logout and new login to take effect): sudo usermod -aG docker osboxes (Re)start docker service: sudo service docker restart Now you can run the command given by Jack before: Enable access to X server: xhost local:root or may better since a bit more restrictive: xhost local:docker Finally run ISE: docker run --entrypoint "ise" -e DISPLAY=$DISPLAY -v /tmp/.X11-unix:/tmp/.X11-unix -v $(pwd):/workspace gassettj/papilio-environment-cloud9 as you can see you have to modify the entrypoint, set the DISPLAY env variable and bind /tmp/.X11-unix - by the way it also works with gassettj/papilio_environment: docker run --entrypoint "ise" -e DISPLAY=$DISPLAY -v /tmp/.X11-unix:/tmp/.X11-unix -v $(pwd):/workspace gassettj/papilio_environment This will start ISE in a window and ask for the license file. [1] https://docs.docker.com/engine/reference/run/#foreground (-it param) [2] https://forums.docker.com/t/docker-run-cannot-be-killed-with-ctrl-c/13108 (docker stop) [3] https://medium.com/@oprearocks/how-to-properly-override-the-entrypoint-using-docker-run-2e081e5feb9d (entrypoint) [4] https://github.com/jessfraz/dockerfiles/issues/6 (xhost) You can also run a bash shell in the docker container for testing and debugging with: docker run -it --entrypoint "/bin/bash" -e DISPLAY=$DISPLAY -v /tmp/.X11-unix:/tmp/.X11-unix -v $(pwd):/workspace gassettj/papilio-environment-cloud9 in order to stop the docker containers (especially with the original entrypoint as Jack set it) use ps to get the container id and then stop it: docker ps docker stop <container> In order to get more info on how the docker image was created, run: docker history gassettj/papilio-environment-cloud9 --no-trunc
  6. Sounds good. Can you elaborate a bit more and explain how I would practically have to do it? I do have basic experience with docker etc. but I have no idea how to modify a container properly...
  7. Hello I have really weird login issues for days now. Basically I cannot login to this forum and my account. Whenever I logout I have to reset my password in order to be able to login again. I even tried copy-n-paste my password from a text-editor, does not work either. I have thus to assume that my password does not get stored properly, may be it's a coding issue - honestly I have no clue... I need help here!! Thanks and Greetings
  8. I like the idea of having a VM to avoid all the install hassle. I finally setup a kubuntu 14.04 VM with DesignLab and ISE. I can offer that VM in case anyone wants it - however the license would have to be removed first. I ran your docker container as explained here and got cloud9 running. How can I run DesignLab and ISE? Is that possible?
  9. Hi Jack, it's been quite some time. Today I did the test of the JTAG variant. One of the reasons why I did not report back for such a long time is that somehow the interplay between DesigLab and Xilinx ISE (Project Navigator, v14.7, lin64) got broken: The edit circuit button in DesignLab does not work anymore for my sketches but for examples (after storing as new sketch of course). Additionaly when I try to open the link sketchdir://circuit/PSL_Papilio_DUO_LX9.xise in my library sketch edit_library.ino file it does not work. But if I run ISE from command line (/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/ise) and try to open the file .../circuit/PSL_Papilio_DUO_LX9.xise from there, it works for most of them. For some of the .xise files I see a huge bunch of libraries in Design tab opened (not only Papilio_DUO_LX9 and Utility). So to me it looks like the interplay of DesignLab with ISE has issuesmay be some files for ISE are corrupt know (but my git repo shows no changes)Is there a way to reset to "factory settings"? Back to the important part, the test of LogicAnalyzer (JTAG variant): As in papilio-prog (ioftdi.h) the USB VENDOR and DEVICE are hard coded, I had first to the adopt ioftdi.h line 37 to reflect correct DEVICE (use lsusb to be sure, it starts with 0403:....) and then recompile it. After that it worked and as I interpret the output connected correctly, the OLS worked but showed only 'zeros'. Looking at papilio-prog console output showed: [...] Start Capture Taking too long, aborting and just sending zeroes. End Capture Closing socket So what am I doing wrong? Why is the capture taking too long? (I think I tried it w/o trigger as well) Greetings
  10. DrTrigon

    Wishbone version of the Sump Blaze Logic Analyzer

    Hi Jack, Hi Alvie This looks VERY interesting and could have saved me some work! Sounds like it could be exactly what I was looking for. How would the data transfer to the computer be done? Serial line (USB)? Would this occupy the serial bus? Or could it run in parallel to serial debug output? (Does it use the "JTAG channel"?) (Will this enhanced memory through DMA thingy also become available to other Logic Analyzer implementations as well? Or will this Wishbone Logic Analyzer be the recommended variant for future use?) How can I upgrade by DesigLab setup in order to be able to use such a new library/code? Just clone it to the "libraries" folder? Anything else needed? Sorry for asking that many questions at once. May be some are asked to early. Thanks for this new library! Greetings.
  11. Hello Jack! Thanks for your detailed answers! Sorry for not answering - I had a busy time, then holidays and meanwhile a few quadrocopters arrived... ) No, we are not seeing the same thing - you might be confusing "Benchy_Sump_LogicAnalyzer_Standalone" and "Benchy_Sump_LogicAnalyzer" examples. In my DesignLab 1.0.7 (and all my posts) the example you mentioned above is called "Benchy_Sump_LogicAnalyzer". The example called "Benchy_Sump_LogicAnalyzer_Standalone" looks like: and the sketch reads: int counter = 0; void setup() { // put your setup code here, to run once: Serial1.begin(115200); } void loop() { // put your main code here, to run repeatedly: Serial1.write(counter); counter++; delay(1); } (this is the full code, not abbreviated) This is exactly like the Arduino example I was mentioning in a post before, right? So I am still wondering the questions asked before regarding the "Benchy_Sump_LogicAnalyzer_Standalone" as shown here. (especially the rxd, txd, RXD, TXD markers confuse me Good hint thanks! Have to read through this as well. Now I have to sit down and do/test these 2 variants finally... ) Greetings & all the best
  12. ) I exactly know this problem... Oh... cool! Thanks for the links, I had a look at it - this is what I did: download and unpack https://github.com/GadgetFactory/Papilio-Loader/archive/debugMode.zipedit .../Papilio-Loader-debugMode/papilio-prog/progalgspi.cpp, line 957:- int sin_size; + socklen_t sin_size; in order to solve: progalgspi.cpp:995:69: error: invalid conversion from ‘int*’ to ‘socklen_t* {aka unsigned int*}’ [-fpermissive] connected = accept(sock, (struct sockaddr *)&client_addr,&sin_size); then follow instructions in .../Papilio-Loader-debugMode/papilio-prog/README:$ sudo apt-get install git autogen automake g++ libftdi-dev $ ./autogen.sh $ ./configure && make after that I had a binary called .../Papilio-Loader-debugMode/papilio-prog/papilio-prog (not butterflyprog as mentioned in the README). So first thing is to check whether it runs: $ ./papilio-prog -h Usage:./papilio-prog [-v] [-j] [-f <bitfile>] [-b <bitfile>] [-s e|v|p|a] [-c] [-C] [-r] [-A <addr>:<binfile>] -h print this help -v verbose output -j Detect JTAG chain, nothing else -d FTDI device name -f <bitfile> Main bit file -b <bitfile> bscan_spi bit file (enables spi access via JTAG) -s [e|v|p|a] SPI Flash options: e=Erase Only, v=Verify Only, p=Program Only or a=ALL (Default) -c Display current status of FPGA -C Display STAT Register of FPGA -r Trigger a reconfiguration of FPGA -p JTAG passthrough mode -a <addr>:<binfile> Append binary file at addr (in hex) -A <addr>:<binfile> Append binary file at addr, bit reversed Ok, yes it runs and comparing this part of the binary against .../DesignLab-1.0.7/tools/papilio-prog-jtag-server/papilio-prog-jtag-server.exe gives me the impression these are the same programs, right? Now the question to me is how to use this binary? From the links you posted I would be temped to run the -p (passthrough mode) but from the Benchy_Sump_LogicAnalyzer_JTAG example, I would think I have to run it without parameters: For Windows: tools://papilio-prog-jtag-server/papilio-prog-jtag-server.exe Thanks for this hint, are you referring to the Benchy_Sump_LogicAnalyzer_Standalone example? Here I am a bit confused by 2 things: Here the markers used are called "rxd" and "txd". How are they related to "RXD" "TXD"? This boils down to the question of what serial port gets used?The code does no serial forwarding. Again what serial port is used? The FPGA one? For me this one is occupied by ZPUino, right?Thanks a lot!
  13. Hello Jack! What's the plan about a release of a linux solution for the JTAG server and Logic Analyzer client software? What is "Coming soon"? I had a look for linux JTAG servers, I found; Altera and UrJTAG (last update 2009) - so I don't know what to do here right now. I tried to use the RXD and TXD markers, like: which resulted in 2 mapping errors: ERROR:Pack:2811 - Directed packing was unable to obey the user design constraints (LOC=P46) which requires the combination of the symbols listed below to be packed into a single IOB component. The directed pack was not possible because: More than one pad symbol. The symbols involved are: BUF symbol "RXD_IBUF" (Output Signal = RXD_IBUF) PAD symbol "RXD" (Pad Signal = RXD) PAD symbol "ext_pins_in<2>" (Pad Signal = ext_pins_in<2>) ERROR:Pack:2811 - Directed packing was unable to obey the user design constraints (LOC=P141) which requires the combination of the symbols listed below to be packed into a single IOB component. The directed pack was not possible because: More than one pad symbol. The symbols involved are: BUF symbol "TXD_OBUF" (Output Signal = TXD) PAD symbol "TXD" (Pad Signal = TXD) PAD symbol "ext_pins_out<25>" (Pad Signal = ext_pins_out<25>) so I went for the Arduino pin markers as: which synthesized well. Next I will run a sketch like the Arduino Mega serial example code (very similar to the Benchy_Sump_LogicAnalyzer sketch) in order to forward the serial data as mentioned. Will keep you informed... Thanks for your help and Greetings
  14. I had a short look and from that as well from what you describe, I think that is the solution to my question - I will test this as soon as possible! Thanks! Though just out of curiosity; would the solution I proposed before work as well? Good point; I'm running Linux. Parts of the reason why I love the Papilio DUO so much is it's Linux compatibility.
  15. Hello Jack Where do the RXD and TXD marker connect to? (Arduino_0 and Arduino_1? Did you change the COM port used in the example video?) I need to have a Logic Analyzer in my ds1wm design for testing and debugging. Thus I had a look at the Benchy_Sump_LogicAnalyzer example. It uses a COMM_zpuino_wb_UART to connect the logic analyzer to the zpuino together with some code that forwards the serial data to and from USB serial port. The problem is that I need the same USB connection (from zpuino) to print debug data to console/monitor. So the question is how to connect the logic analyzer to the ATmega Serial1 port (and use it's USB serial connection) instead? Is ATmega Serial1 fast enough? Is such a connection established by using RXD and TXD? What physical connection/pin do RXD and TXD utilize? Thanks and Greetings DrTrigon