Hi, my name is Patrick and I am a computer scientist. I am starting to dive a bit into FPGAs (and in my case VHDL). So after doing some basic stuff, I wanna try to emulate a ROM IC for an old german gaming console much like the Atari 2600. So the task is basically turning an 11 bit address input into (the correct) 8 bit data output aswell as matching/shifting the levels (5V to 3.3V (input into Papilio), 3.3V to 5V (output of Papilio)) and fulfill the right timing constraint (~400ns between adress input and data output). I used an IP Core/Vendor module (Block memory generator/Single port ROM) for the ROM memory and initialized it with a COE file. In the simulator everything is working fine and i can see the change of the data output according to the change of the address input change. But when I look into the generated BIT file I cannot see that the data from the COE file is embedded in it. I cannot find e.g. the first two byte sequence in the BIT file. So my question is: Is the ROM initialization (COE file) embedded into the BIT file or do I need to so some extra steps such that the ROM initialization is embeeded into the configuration/BIT file. Is this even possible since due to the "black box"-warning of the Xlinix ISE I guess nothing for the ROM module is even generated into the BIT file? Sorry, if this is a beginners question.