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About cawhitley

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  1. cawhitley

    Fast internal clock on DUO

    Thanks for all the specific info guys. Great food for thought. Over the past couple of days, a thought came to me of how to reduce the data throughput requirement, which may allow me to eliminate the need for BRAM completely, and thus allow me to optimize the code more. Hopefully, I can can a faster, more reliable design.
  2. cawhitley

    Ethernet Wing Speed

    Thank you. That helps. Meanwhile, a thought came to me of how to reduce the data throughput requirement of the project, so slower speeds may be okay. :-)
  3. cawhitley

    Fast internal clock on DUO

    Well, I had my wires crossed! What IS working right now is the serial communication (RX pin), on which I am sending data from a PC at 3.4 Mbps. What is NOT apparently working is the BRAM, because the data that come over are kept in BRAM, then used by the state machine. The data do not appear to be correct. So maybe 248 MHz internal clock is too fast for the BRAM? Strange, since the BRAM has a limit of 300+ MHz. But there are probably things involved that I know nothing about. :-)
  4. cawhitley

    Fast internal clock on DUO

    FYI, this whole FPGA concept is pretty new to me. I used one years ago, but had an EE standing next to me, helping me to go through the design/build process. This is the first time that I have taken on a real VHDL coding project. I was able to use the PLL to get a clock speed of 248 MHz, which is pretty nice. I believe the clock can go faster with very simple logic, but I read in a flyer for the Spartan 6 that its BRAM is limited to 300+ MHz, and it appears that if I approach 300 (say, 288), things get hairy. Build results show this, although I'm unsure what it all means. What does the max frequency represent? Timing Summary:---------------Speed Grade: -2 Minimum period: 47.081ns (Maximum Frequency: 21.240MHz) Minimum input arrival time before clock: 2.009ns Maximum output required time after clock: 5.220ns Maximum combinational path delay: No path found I had this dream of using a 1 GHz internal clock, but I did not realize that very parts (guts) of the FPGA have distinct speed limits (e.g., BRAM, multipliers, i/o, etc.) Since things are generally working at the moment, I will try to stick with the speed that I have. thanks!
  5. cawhitley

    Fast internal clock on DUO

    Has anyone attempted to use a fast internal clock speed on the DUO? I tried to use the clk_32to960_pll.vhd entity (via its symbol), but the resulting clock is not stable, as far as I can tell. The two methods that I tested that with are (1) serial communications, and (2) watching a blinking LED. As far as I can tell, theoretically, the Spartan 6 can run at up to 1 GHz internally. For a 32 MHz input clock, the PLL would need a multiplier of 32 to reach 1 GHz. So, I am asking whether anyone has had success using such a fast clock rate (i.e., faster than about 375 MHz). Thanks!
  6. What is the maximum data transfer rate of the Ethernet Wing (in Mbps or MBps), counting any necessary SPI start/stop delays? I may wish to get data from it at around 25 Mbps, if possible. I refer to this one: thank you!!
  7. cawhitley

    DCM not working on P-One

    Thanks, offroad. I already did divide it by 16, 8, and 4, and verified that I could see the clock on the scope. I am now beyond that one issue, on to deeper stuff in my VHDL application.
  8. cawhitley

    DCM not working on P-One

    James, I am using an SDS200, which is a USB scope. Someday, I need to get a "real" scope. That one can run up to 5 GHz for sampling, but I am unsure of its maximum displayable speed in MHz. When I divided down the 288 MHz clock to 72 MHz, I could see the wave. Have not tried anything higher (other than 288 itself). I was just verifying that the DCM was working.
  9. cawhitley

    DCM not working on P-One

    Alvie, your advice worked. Thank you. One thing that I still don't understand is why I could not send the 288 MHz signal directly out one of the output pins, so that I could o-scope it. I had to divide it down, and then scope the divided clock. According to the Spartan 3E doc, the i/o should support up to 622 MHz, but apparently it does not. I am not an EE, but an embedded programmer, so I'm not sure about why I could not measure the 288 MHz clock. In any case, there is a fast internal clock now.
  10. cawhitley

    DCM not working on P-One

    Thank you aliveboy! I do recall that in one iteration of my trials, I used CLKFX, but things still did not work; however, it may be that they did not work for some other (unknown to me) reason. Once I tried using CLK0, the rest is history; I would never have the proper clock output after that point. So, I will give your advice a try. Thanks again.
  11. cawhitley

    DCM not working on P-One

    I have tried various ways to get a higher clock speed than 32 MHz on the Papilio One. I generated the DCM VHD file using the Core generator. I tried it with and without feedback. In all of my testing, I never got anything except a 32 MHz clock output, which I sent to a P-1 pin, so that I could check it. Can anyone please tell me how to get the DCM to function correctly, to output a high-speed clock? I tried the standard 288 MHz one from the library, but it did not work, either. Bottom line, I cannot get a 288 MHz clock, only a 32 MHz clock. Please help! Thanks. clk_288_mhz_w_fb.vhd