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About Speeder

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  1. Speeder

    Papilio one check if it is okay

    I can see it now. But I can still add the same VHDL source to papilio one and it should work right?
  2. Speeder

    Papilio one check if it is okay

    Hi, Thanks for the reply. I opened it up with design lab and looked at the ZPUINO file. There doesnt seem to be any logic analyzer module connected to it. I opened the Camera7670.ino using design lab and clicked edit circuit. Now in Xilinx, where should i look for the analyzer module? I am not able to find the source for the .ngc blackbox file. Is it located in this? What is the huge 200 pin wing coming into ZPUINO?
  3. That looks very interesting. I will definitely look into it. Thanks for the help.
  4. Speeder

    Papilio one check if it is okay

    @treadstone, yes, That is definitely one way to do it. I did try that though. However I am still unsure as to whether glitches can be caused by the problem you mentioned. @jack, could you upload the remaining files you have used as a reference in the project. There seems to be alot of files which are not found. Also , I am more interesed in using this like chipscope where I would like to call it in VHDL. Is there some files that need to be added? I already have a project. I dont want to bring out the pins on the papilio as logic analyzer pins. Instead I want to internally connect them to view it. Could you please help me out?
  5. That is going to be really hard to do. Anyway , thanks for the help.
  6. Speeder

    Papilio one check if it is okay

    How can I embed the sump logic analyzer into my design? Is there any tutorial for this ? Where would I find the module to insert into my VHDL?
  7. How do I hold the FPGA in reset state?
  8. Speeder

    Papilio one check if it is okay

    I am using a salae logic analyzer at 24Mhz.
  9. Hi, I am trying to use the Papilio loader to program an FPGA which has only JTAG pins. Do you have any ideas as to whether this would work if I have bought a FT2232 board? If I use the JTAG header on an existing papilio one and connect the jtag signals to another FPGA will that FPGA also be programmed with the same bitfiles which I am using to program the current FPGA?
  10. Hi, I have a papilio one and am using it for getting data from an OV7670. However after several attempts , I observe that the VSYNC from the camera comes into the papilio correctly , but this same VSYNC(without any modification) if latched and sent to another pin seems to have many glitches. This is surprising since the simulation shows no problem and the VSYNC is coming corrctly. It is also a low frequency signal . Is there any way I can check to see if the Papilio is okay, and if there are some problems on the board itself? COuld you upload the bitfile I give you and check if you are seeing the same problem? Please let me know how to proceed.