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jezsmith41 last won the day on August 6 2015

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About jezsmith41

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  1. jezsmith41

    Altera Intel impacts

    It has to be said however that the poor error messages are more down to the lrm rather than the tools
  2. jezsmith41

    Altera Intel impacts

    Its true all logic compilers are bad at producing relevant error messages and can lead users on a wild goose chase, the most common message being 'its broken and I am not telling you why'
  3. jezsmith41

    Altera Intel impacts

    The open source fantasy that people are interested in modifying tools when they have got work to do is nothing more than Stallman driven drivel.
  4. jezsmith41

    Altera Intel impacts

    Project ice storm is complete nonesence, basically because no working engineer is in the slightest bit interested in spending months delving into code, trying to work out how it does what it does, and then adding some mystical new feature which is going to open up hitherto unexplored vistas of wonderousness, doing all this without breaking the code, it ain't gonna happen when every major vendor supplies working synthesis tools which do what they say on the tin and took many hundreds of man years to write
  5. jezsmith41

    VGA image editing

    Given that I nearly smacked a Linux weeny very hard in the mouth this morning because of his patronising attitude and his overriding obsession with the wittering of the paranoid delusional tramp that is Richard Stallman, I am quite glad I don't use linux
  6. jezsmith41

    S/PDIF interface

    I also hacked his Mandelbrot project and added some extremely cunning speedups for corner cases when you can show that a point is never going to converge algebraically, I really need to put my server back together
  7. jezsmith41

    S/PDIF interface

    I did incorporate hammy's code into an audio DSP design I was playing with a while back, I'll have promised to post it sometime although I should warn its in VHDL which is what cool kids code in.
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  9. jezsmith41


    The other thing to consider is that if your design is subject to change then an FPGA is far easier to deal with than respinning an asic
  10. jezsmith41


    The economies of scale don't kick in until you are using a few thousand devices a month and your design is fully fixed, there are some FPGA families which are designed to have a slightly easier path to full asic implementation.
  11. jezsmith41


    You would be looking at £100,000 plus for an asic plus 6 months work, which is why people prototype asics using fpgas