dindea

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About dindea

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  1. dindea

    Flash Erase

    Thank you for the info, Thomas Hornschuh. It was as I hoped. But what do you mean by "Normally"? Are there cases when the entire flash is erased? Anybody who knows or has an idea about the "worst-case" size of a SPARTAN6-LX9 bitstream? I.e. the size of the bitstream for the largest possible SPARTAN6-LX9 application.
  2. dindea

    Flash Erase

    Programming the flash of Papilio PRO with a new FPGA application will require erasing the flash or a part of it. My question is: How much will be erased? The entire flash or only so many blocks that the application will occupy? Or "something in between", e.g. "always 2 MBits"? Or the number of blocks occupied ny the greatest possible application for SPARTAN6, by assumption different for ...LX4 and ...LX9?
  3. dindea

    Contradiction in description

    Hi, In my 'Mariposa S6' design, I have inserted buffers at the TMS and TCK inputs of the FPGA. The buffers are enabled/disabled by a "JTAG disable" pin on the board. The purpose of these buffers was from the beginning a "security lock" against "accidental" programming (changes of the FPGA code), e.g. because of contact bounces when the unit is powered-on and/or the JTAG cable is plugged-in or unplugged. The enable is delayed with a RC lag. The signal paths from the JTAG circuit to the JTAG connector are still intact when the buffers are disabled. This means that the Mariposa S6 can be used as a "universal" JTAG programmer for other devices, also when "he" is up and running. I think that you could fix such a feature to use the Papilio Pro as a "universal" JTAG programmer. Solder a couple of patch wires, to the FPGA's 'INIT_B' pin and GND, glue a 2-pole connector "somewhere" on the board. Insert a jumper to hold the FPGA "permanently" reset. See attached schematics. The signal paths from USB circuit to JTAG connector will be "un-touched". On the Papilio One the INIT_B pin is a multi-funcyional pin. It will be 'INIT_B' as long as the FPGA code is not uploaded, it becomes 'W1-B15' when the code is uploaded. Certainly: Connect it to GND before power-on. Then, certainly, the FPGA will be held in "permanent" reset. Signal paths from USB circuit to JTAG connector will be "un-touched". Both boards: When the FPGA is held in permanent reset, the board can be used aas a general JTAG programming adapter. /SC JTAGpatch.pdf
  4. dindea

    Contradiction in description

    I have double-checked. MPSSE is supported on channel B. How are the Flash data trnsferred to the Papilio Pro? Over the JTAG interface of ch.A or over the ASYNC (RS232) interface of ch.B? Is it a "bootstrap" procedure, where a "bootstrap" is first uploaded in the FPGA, this "bootstrap" then reading data from JTAG or ASYNC (which?) and writing into Flash. Will Developement Studio unravel a situation where the A and B channels have changed places? SC
  5. dindea

    Contradiction in description

    The description (on 'papilio.cc') text for Papilio PRO "says": Channel A is connected to the Papilio Pro in an Asynchronous serial UART configuration that is capable of speeds up to 2MHz. Channel B is connected to the JTAG pins of the Papilio Pro and provides very fast programming of the FPGA (500mS). But I think that the USB schematic right below the text "says" the reverse. The JTAG-s go to ADBUS0..3, TXD abd RXD go to BDBUS0..1. And so says the published complete schematics for Papilio PRO. I am designing an own board based on ideas from the Papilio PRO schematics. I would rather really use Channel B for JTAG and channel A for data transfer. For then I can, with FT2232H as USB ctircuit, use synchronous FIFO245 for general data transfer. Only Channel A (FT2232H) supports synchronous FIFO245. How is the FPGA code uploaded into the flash? Is it all over the JTAG interface, or is it by implanting an application which reads data from the UART (RS) channel, writing them into the flash memory word by word? If the second is the truth, can Developement Studio handle the "reversed" USB addresses (COM ports, or...?)?
  6. dindea

    Physical dimensions, mechanical drawing

    I think I have "found something" on FTDI's web page. Anyone who has a EEPROM template for Papilio ONE or PRO? /dindea
  7. dindea

    Physical dimensions, mechanical drawing

    (maybe not relevant to call this a "reply", but...) The USB interface in the designs ('ONE', 'PRO') needs a configuration EEPROM. How is that EEPROM loaded with relevant contents? With the Papilio software? Or... ? I assume it's the EEPROM that defines how the interface is configured, that channel A runs as a JTAG interface, channel B as a RS232(-like) interface. Wrong? How can the hardware outside the USB interface see when the Tx buffer is full? /dindea
  8. dindea

    Physical dimensions, mechanical drawing

    OK, it was a little of a mistake. I have looked at the 'PRO', too. The I/O connectors (WING1, WING2), and the adjacent 4x1-s for supply voltages, form the same pattern as on the 'ONE'. Same distances. The PWRIN connector has the coordinates (16.51, 40.64) instead of the (10.414, 40.142) on 'ONE'. So if I mount PWRIN mates at both (16.51, 40.64) and (10.414, 40.142), both boards will fit. No care taken (yet) to the different outer dimensions of the boards. The 'PRO' board extends another (some) 16mm below the W2_A16, W1_B16, W1_A1 pins. One more thing, when/if I build the FPGA interface myself on the motherboard: A configuration EEPROM is connected to the USB circuit. If I build an interface myself, the EEPROM will of course be initially blank. I assume the EEPROM on the 'ONE' and 'PRO' boards has relevant contents. How do I load relevant contents into "my own" EEPROM? /dindea
  9. dindea

    Physical dimensions, mechanical drawing

    Doug (and others), I downloaded and installed EAGLE as freeware, so I could read the '.brd' file correctly. From that I made a "mechanical" drawing of the board, seen from the "component side". See attached 'papilio_one.pdf'. The drawing contains coordinates of the "mass centers" of connectors relatively to the single-row 16-way connector. I could look at the schematics, too. But I wonder if it is complete? I do not find all the connections for supply voltages in the diagram. And there is supply voltage "5V0" referred, with a '+' inside a ring. I find no source for '5V0'. If, as I have plans to do, install Papilio ONE as a "piggy-back" board on a motherboard, I assume I can feed it with 5V from the motherboard via the supply-voltage connectors (those with 5V, 3.3V, 2.5V and GND), not installing the 'PWRSELECT' jumper (normally selecting whether to take 5V from USB or the built-in voltage regulator) and leaving PWR1 and PWRIN unconnected. This is a conclusion from the Schematic. I think it would not be too difficult to replace the sleeve connectors on the "component side" with pin connectors on the "solder side", to mate sleeve connectors on the motherboard. BTW, I think that the Schematic tells me how I could myself include the USB circuit, the FPGA, etc. on my own motherboard, without a 'Papilio ONE'... /dindea papilio_one.pdf
  10. dindea

    Physical dimensions, mechanical drawing

    Thank you, Doug L and Felix! The question is fully answered, case cloced. With thanks /dindea
  11. Anybody who has a mechanical drawing with all measures between connectors, mounting holes, etc? I have plans to use a Papilio PRO as a piggy-back board on a "mother board". Therefore I need to know the exact placements of the connectors. ("Future will show" whether I keep the females and turn the board upside down into males on the board, or replace the top-side females with bottom-side males fitting into females on the mother board)
  12. dindea

    Physical dimensions?

    Anybody who has a mechanical drawing with all measures between connectors, mounting holes, etc? I have plans to use a Papilio ONE as a piggy-back board on a "mother board". Therefore I need to know the exact placements of the connectors. ("Future will show" whether I keep the females and turn the board upside down into males on the board, or replace the top-side females with bottom-side males fitting into females on the mother board) /dindea