Polygonhell

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About Polygonhell

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  1. arty $99 artix fpga board

    I picked one of these Arty boards up, I have to say I find Vivado to be an improvement over ISE. We'll see how that pans out after the year of support expires. Rather bizarrely ISE only supports the higher end Artix7 boards, so it's not an option at all. All in all a nice board for $100, though a lack of available video connectors is a bit of a downer, not that it's particularly difficult to throw something together.
  2. How about designing a video game console?

    Based just on how much real-estate is needed for even simple 8 bit processors, my guess is you'd need something bigger than the LX9 in the Papilio to get something close to a PS1 or Saturn, the Pipistrello is an LX45 which is pretty much as big as you can go with the free tools, my guess is that might get you close in terms of needed resources. As others have said it's probably not a good starter project. But certainly something interesting to aim at. I did game development for 25+ years and I'd consider myself a pretty proficient developer, but it's taken me a lot longer to get my head around FPGA programming than I thought it would. Learning Verilog or VHDL is the easy bit, getting my head around what a piece of Verilog or VHDL is turned into took me months. There is a tendency to treat it like software when you start, but you really do have to consider what it is your describing to get a good (or often just working) implementation.
  3. Using SDRAM like if it was SRAM, again

    What clock speed are you running the spectrum at? And how are you getting the data across the clock domains?
  4. Using SDRAM like if it was SRAM, again

    Your really just looking to see that the control lines are behaving the way you expect.
  5. Using SDRAM like if it was SRAM, again

    FWIW I don't see an obvious error in your code, but I will say I've written code that looked fine to me, but didn't generate the hardware I expected, pretty much the only way to know what your actually getting is looking at the simulator. Coming from a software background when I first started with FPGA's I treated it like developing software, it wasn't until I started trying to build something none trivial I started to realize just how different it was, I've seen the tools remove what to me was obviously in use logic resulting in state machines that didn't cycle through states as I'd expected. Now I start with a test bench and check it in the simulator before I even try it in hardware. If it doesn't work in the simulator it won't work in hardware.
  6. Using SDRAM like if it was SRAM, again

    Your best bet for debugging this is using the simulator. If your running on multiple clock domains it's often hard to understand how things interact. Hamsters Controller certainly does work, I looked at it probably 3 months ago just before I wrote my own.
  7. Altera Intel impacts

    Without getting too far down the open source rabbit hole. The license matters as do the interested parties. GCC has seen a dramatic drop off in contributors since they swapped licenses to GPL V3, no vendor dares use the V3 versions in a commercial product. Which is why you see vendors stuck on earlier GCC releases and the move to LLVM and Clang. Most of the successful large scale "Open Source" projects are so because they are largely written by the commercial entities consuming them. It also tends to be their biggest weakness, all the major contributors have agendas, and if your use of the tool isn;t aligned with their vision for it, best of luck actually getting a change for your use case accepted. When I first used the Xilinx tools I was stunned that they could get away with shipping ISE, it's usability is horrid, last night I downloaded the Lattice Semi tools and discovered they were even worse. I'm sure the underlying code generation portions are quite good, but there is just no thought put into how people interact with them. Any real competition in the space seems like it would be a win.
  8. Altera Intel impacts

    I suspect Intel sees an increase in the use of FPGA's in the embedded space, and they are looking for a way to compete with the ARM + FPGA devices that are around. The other possibility is the recent attention FPGA's are getting in the High Performance Computing space. I agree the biggest winner here is probably Xilinx, even if Intel is committed to investing in Altera, it will minimally derail their roadmap.
  9. Webpack is pretty much complete, you can write either Verilog of VHDL, you can't redistribute the Xilinx provided IP blocks, and I believe simulation performance is crippled.
  10. Material for understanding IOBUF and clock routing

    Thanks again, So for the most part it's just a stylistic difference, then I will continue just putting the + in the process unless I need access to it in multiple locations. I find it easy to pick up the syntax of new languages, but understanding idiomatic usage takes time, having a lot of fun with the papilio, I think a lot of programmers would get something out of implementing all the basic building blocks. Certainly building the DRAM controller was a great way to reinforce the way DRAM behaves.
  11. Material for understanding IOBUF and clock routing

    Thanks, that t least gives me a starting point for building some sort of mental model. I had another question I often see code that does something like the following counterNext <= counter + 1;someProc : process (clock) begin if rising_edge (clock) counter <= counterNext; end if;end process;My assumption is this is done to reduce the skew on the counter relative to the clock because it moves the add outside of the synchronous process. Is my assumption correct here? or is there some other reason to write it this way rather than putting the add inside the process? Thanks
  12. I got my papilio pro board a couple of weeks ago, I'm an experience programmer but I'm new to FPGA, I've read a couple of books on VHDL, and for the most part I understand the basics, I spent the last couple of days implementing an SDRAM controller. I did finally get it working, but it became really apparent my understanding of when to use OBUF's, BUFG's etc etc, was at best an educated guess. Is there a good discussion on when and why to use the SelectIO resources, I've read the Xilinx piece, but while I think I understand what they are, I have no intuition on when or why to use them. Thanks