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Everything posted by nilrods

  1. nilrods

    Working on Papilio Nano

    Jack, Just saw this. Looks like a great idea to me. Count me in for a couple when you get them going. I like the idea of the keeping the optional components like memory separate if you don't need them. Chris
  2. nilrods

    arty $99 artix fpga board

    Not sure if anyone saw this one yet. It is vivado based. Looks like a decent board. Looks like avnet and digilent are putting this one out. Nice to see one for less than $100 without requiring being student. Any thoughts? Thanks, Chris
  3. Jack, How was the trip to China? Did anything new for the papilio platform come out of it? Chris
  4. nilrods

    Jack how was China Trip

    Wow that sounds like a cool project.
  5. A new ZYNQ board with wifi built-in starts at $55 per board. I had emailed with the guys who started this project a while back. Sounds like a good project. I have no idea how they can sell these that cheap. The loading configurations via a phone could be really nice way to deploy solutions. Seem to be really focused on flight/drones and computer vision Z7010 and Z7020 version Dual core Cortex-A9 hard processors 512 or 1204 LPDDR memory wifi Bluetooth classic and low energy 100+ GPIO Curious what other think about this one. Thanks, Chris
  6. John, I seem to remember the PowerPC CPU being pretty good too. I believe IBM used to use those on their midrange unix servers years ago, not sure if they still do. With the Zynq I believe there are multiple boot options for programming fpga and all(at least from what I read in the TRM). I have been using the config where the bit file is in the initial boot file along with the first stage bootloader(FSB) and Linux u-boot. I believe the first stage bootloader loads the FPGA image, but I could be remembering incorrectly.
  7. Alvie, Nice. Looks like some nice features with the 64bit ARM and ARM cortex R and all. I wonder how long before we see a reasonable board with one of those on it. Thanks, Chris
  8. Jack, Yeah I would agree. I think it is a tall order and they can't be making any money doing it. They must have some sort of plan for generating income from other methods to support it. Hopefully it pans out though. John, I don't know the kind of projects you work on, but for the ones I working on the $55 board with like $15 is connectors and wires would work fine for me. Most of the projects I am working on only require networking and GPIO. I would agree on the open source term. I think probably they are referring to their app and configurator and the hardware being open source, just like designlab is open source but ISE is not. But I think you are 100% correct that all Zynq use closed source for the FPGA portion at least. Of course, the Linux that runs on the ARM's hard processors is open source so possibly if you don't use the FPGA fabric it could be considered open source, but to me that defeats the purpose of using a Zynq board, might as well just use a cheaper ARM. What I hope works out is their app for configuration and deploying solutions, if they get enough of solutions to chose from. If anyone has worked on a Zynq project, one that is more than just loading an demo image, all I can say the process is tedious at best. I have one configuration that I have petalinux on CPU0 and bare metal on CPU1(AMP config) plus FPGA logic. Very tedious to build the multiple board support packages, bootloaders, drivers, on top of normal code and keep it all in sync so it all builds. Just my thoughts. Thanks, Chris
  9. Alvie, Good point and info. Thankfully most of my applications are not battery powered. I liked the $55 or $60 price tag. I also have a parallela but they have gone way up in price for boards now. Thanks, Chris
  10. nilrods

    arty $99 artix fpga board

    I too would like to see an artix papilio. What would design lab look like with Vivado vs the current ISE? I have been playing with the vivado on a zynq board. I think it would integrate nicely with designlab since the block designs already resemble the schematic design to me in ise. As to the point that keeps coming up with development boards about licensing and not open source. The point is these are for profit companies not charities. i would venture to say they are making money off the current licensing models and as long as they are then they will never make them opensource. That is just business and until some other company comes along to force them by open sourcing their tools I don't see it happening anytime soon.
  11. nilrods

    Cubic Board FPGA

    Not sure if anyone has seen this one yet . It is an Altera board but I think it is a nice design. It is built by some Altera engineers, but not an Altera officially sanctioned project. I really like the way they separated the core board that you can use in your own designs from all the other boards. As I have mentioned before I like the core board/modular idea, which sounds like what the original papilio board was. It is open source also. It is like a parallella or other zynq board but has Altera fpga. I had sent an email to the project a while back about availability and heard back that I guess Terasic is reviewing it to possibly offer them for sale. Hopefully the price doesn't go way up over what they were originally targeting for price. I like that it is open source but looks to be well beyond my skills soldering the bga and all. Curious what others think about it and eventually what the pricing will be. Thanks, Chris
  12. nilrods

    Cubic Board FPGA

    James, I had seen discussions of the MIST board on other sites before also. For some reason I always thought it was a Xilinx Spartan board. Good to know. Thanks, Chris
  13. nilrods

    Cubic Board FPGA

    Jack, Yeah I saw that one too... They must have not looked too hard. Maybe they are referencing specific to Altera??? Thanks, Chris
  14. nilrods

    VDHL signal module question

    Jack, Thanks for the info. Actually the controlReg0 and statusReg1 were not ports in the top level module, the only top level module port was the bus, which is why I didn't include in the top level port command I posted in the first message. So controlReg0 and statusReg1 were just signals defined in the top level module. They were used in the port command for the submodule though. That was what was so confusing about the code. It was much different than what I have seen how a lot of the wishbone vhdl code handles buses. The way I read it was that the bus is the only thing coming into the top level module. Then the bus and the registers are in the port to the sub module. It was like they designed the submodule to handle processing the registers. I think I will just build up a minimal test with a microblaze and try it out to see how it works and why they built it that way. Thanks to you and Alvie for the info, Chris
  15. I had a VHDL question for any of the gurus out there. I am sure the issue is my mindset coming from a software background. Hopefully someone can set me straight. I am trying to understand some Xilinx AXI bus code that seems to process the AXI registers in a submodule of the top module. Say I have a top level module and another sub module that is instantiated from the top level module. The sub module has ports for a bus and one or more registers. entity submod port ( controlReg0 --Register to send control signals statusReg1 --register to return current operating status bus -- multiple bus signals but just being high level here ); Internally this sub module processes bus signals and stores register updates that come over the bus to the registers In the top module entity topmodule port( bus --multiple bus signals but just being high level here ); Now within the top module code there are signals say reg0 and reg1 defined. Within the top module code it instantiates the submodule like so. test : submod port map ( reg0 => controlReg0, reg1 => statusReg1, bus=>bus ) In this scenario are the reg0 in the top module and the controlReg0 in the submodule actually the same or are they 2 different actual entities. What I mean is when some data is sent over the bus and the value of controlReg0 is changed in the submodule is the value of reg0 also changed or do I need to do a specific assignment? And vice versa if the value of reg0 is changed in the top level module is that value reflected in the next read of the controlReg0 over the bus? I think it looks like they are just 2 different references to the same register since in the port I set then to be the assigned to each other, but I could be way off here. Not sure how this is all handled once it is translated to hardware. Any insight would be helpful. Thanks, Chris
  16. nilrods

    VDHL signal module question

    Alvie, Sorry I had left them off for brevity. Yes controlReg0 is defined as signal std_logic_vector(31 downto 0) in the top level module and reg0 is defined as signal std_logic_vector(31 downto 0) in the submodule. Basically the register size of the 32 bit bus. The port is defined as OUT for reg0 and IN for reg1 on the submodule and I believe it is synchronous since both top level module and submodule processes are driven by the bus clock signal. I would post the whole code but it was pretty large with pages of other logic around processing on the bus signals and all. I was just trying to simplify the example to just the specific area I was interested in understanding. Any thoughts would be helpful. Thanks, Chris
  17. nilrods

    Altera Intel impacts

    As I am sure some of you have heard Altera has finally agreed to be bought out by Intel. With all the drama that was going on earlier in the year between the two I have to admit I am surprised it went through. What are the thoughts on how this will impact the FPGA landscape? I would think since probably 90+% of pc run Intel processors if they start coupling FPGA's with the processors for specific application acceleration in commodity processors that could really change things. I know there was talk of a Xeon FPGA chip a couple years ago but I never heard it was actually for sale. But if it makes it to the average user or even mid-range processors that could really be big. Think of a Zedboard on steroids... Will this purchase help Altera to become a larger player in the market than Xilinx? Or will Intel owning them just cause Altera issues? Or is it just a matter of time before another chip maker buys Xilinx? Anyway just thought I would see what others thought the impact of this could be. Thanks, Chris
  18. nilrods

    AVR to Wishbone bridge issue

    I am trying to get the example project AVR_WISHBONE_BRIDGE to work. I am finally at a point on a project I need the 2 to talk. I have tried in earlier versions and it does not synthesize. I have also downloaded the latest version of Designlab and it does not work there either. It looks like some change had been made to possibly the ZPUino since it was created that is causing it to fail to build. At this point I have not added any additional code, just opened the example project with DUO as board and edit circuit and then generate programming file. Below is the error . Elaborating entity <AVR_Wishbone_Bridge> (architecture <behave>) from library <designlab>. WARNING:HDLCompiler:89 - "C:\DesignLab-1.0.7\libraries\AVR_Wishbone_Bridge\AVR_Wishbone_Bridge.vhd" Line 168: <zpuino_papilio_duo_v2_blackbox> remains a black-box since it has no binding entity. ERROR:HDLCompiler:410 - "C:\DesignLab-1.0.7\libraries\AVR_Wishbone_Bridge\AVR_Wishbone_Bridge.vhd" Line 246: Expression has 19 elements ; expected 21 I tried just changing the 2 locations where the sram mention 18:0 to 20:0. This does get rid of this error, but then it generates a whole slew of other errors. Has anyone got this to work recently? Is there something small I am just missing? Thanks, Chris
  19. nilrods

    AVR to Wishbone bridge issue

    Sounds good. Thanks Jack. Just figured since I had got confused others might also. Chris
  20. nilrods

    Interesting FPGA board ICARUS

    hehehehe, I thought the same thing myself when I first saw the name. Not sure I would have called an electronics board after a project that ended in flames myself.
  21. I ran across this interesting FPGA board the other day and thought I would share. It was designed for bitcoin mining back when they were still using FPGA's. I saw some new boards, probably closeouts since most bitcoin miners have moved on to ASIC's. From what I read it's primary purpose was bitcoin mining but the guy that came up with the board as designed it to be a development board and sold most of the first batch to developers rather than bitcoin miners. From what I read the board worked well. Here are some basic specs - 2X Spartan 6 LX150, 100+ GPIO(looks like in DIMM form factor) 50+ interconnect wires between the 2 Spartan 6 most routed as differential pairs. The board is open sourced. I see them right now for sale for like $160, which to me seems ridiculously cheap since the price I see for Spartan 6 LX150 is about that price for one(I am sure they bought on volume at some point in the past). I wonder how much work it would be to add support for a board like that to the DesignLab. Might be great for some of those bigger, more complicated projects. I have my eye on one for an AI project I have been getting interested in. more info Just my thoughts. Thanks, Chris
  22. In case you haven't seen it. Chip the $9 computer has raised almost $1.5 million so far. At that price I am sure that it will be lacking for some functionality. Jack, just a thought any ideas in the queue for an add on shield or something to this one maybe to tie in to the papilio platform? Sounds like over 28,000 customers already. Sounds like they want to be the next raspberry pi... Chris EDIT: corrected my math
  23. nilrods

    AVR to Wishbone bridge issue

    I figured it out finally. I happened to be looking around the gadget factory website and saw there was a video about this topic I had not seen. It uses a new example AVR_to_ZPUino_Communications. It does work fine on the duo. So if anyone else is looking to do this use the AVR_to_ZPUino_Communications example not the AVR_Wishbone_Bridge example. Jack you might want to remove that older example if you get a chance in future versions of DesignLab since it might cause confusion if someone doesn't see this post. Thanks, Chris
  24. Felix, Just in case you decide to use openscad here is an example of how it is used. The attached file is an openscad script with parameters I wrote to create various size hose adapters(like dust collection or vacuum hoses). It is out on thingiverse This file is for a 3d object. So some of the primatives you would call for a 2d object (like laser cut) might be a little different but hopefully it helps you at least see how it is used for a complicated object. Bascically you define multiple shapes based on sizes and then translate(or move) them and join them to create larger shapes. If you get stuck fell free to let me know and I will see if I can help out. hose_adapter.txt Thanks, Chris
  25. Felix, I use openscad. It is free and if your more of a programmer type it is easier to use. You don't draw with it just enter dimensions and shapes via text. It can export dxf for laser cutting 2d shapes or stl files for 3d printing. Not sure if that helps. Thanks, Chris