nilrods

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About nilrods

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  1. Working on Papilio Nano

    Jack, Just saw this. Looks like a great idea to me. Count me in for a couple when you get them going. I like the idea of the keeping the optional components like memory separate if you don't need them. Chris
  2. Jack how was China Trip

    Wow that sounds like a cool project.
  3. Jack, How was the trip to China? Did anything new for the papilio platform come out of it? Chris
  4. John, I seem to remember the PowerPC CPU being pretty good too. I believe IBM used to use those on their midrange unix servers years ago, not sure if they still do. With the Zynq I believe there are multiple boot options for programming fpga and all(at least from what I read in the TRM). I have been using the config where the bit file is in the initial boot file along with the first stage bootloader(FSB) and Linux u-boot. I believe the first stage bootloader loads the FPGA image, but I could be remembering incorrectly.
  5. Alvie, Nice. Looks like some nice features with the 64bit ARM and ARM cortex R and all. I wonder how long before we see a reasonable board with one of those on it. Thanks, Chris
  6. Jack, Yeah I would agree. I think it is a tall order and they can't be making any money doing it. They must have some sort of plan for generating income from other methods to support it. Hopefully it pans out though. John, I don't know the kind of projects you work on, but for the ones I working on the $55 board with like $15 is connectors and wires would work fine for me. Most of the projects I am working on only require networking and GPIO. I would agree on the open source term. I think probably they are referring to their app and configurator and the hardware being open source, just like designlab is open source but ISE is not. But I think you are 100% correct that all Zynq use closed source for the FPGA portion at least. Of course, the Linux that runs on the ARM's hard processors is open source so possibly if you don't use the FPGA fabric it could be considered open source, but to me that defeats the purpose of using a Zynq board, might as well just use a cheaper ARM. What I hope works out is their app for configuration and deploying solutions, if they get enough of solutions to chose from. If anyone has worked on a Zynq project, one that is more than just loading an demo image, all I can say the process is tedious at best. I have one configuration that I have petalinux on CPU0 and bare metal on CPU1(AMP config) plus FPGA logic. Very tedious to build the multiple board support packages, bootloaders, drivers, on top of normal code and keep it all in sync so it all builds. Just my thoughts. Thanks, Chris
  7. Alvie, Good point and info. Thankfully most of my applications are not battery powered. I liked the $55 or $60 price tag. I also have a parallela but they have gone way up in price for boards now. Thanks, Chris
  8. A new ZYNQ board with wifi built-in starts at $55 per board. I had emailed with the guys who started this project a while back. Sounds like a good project. I have no idea how they can sell these that cheap. The loading configurations via a phone could be really nice way to deploy solutions. Seem to be really focused on flight/drones and computer vision Z7010 and Z7020 version Dual core Cortex-A9 hard processors 512 or 1204 LPDDR memory wifi Bluetooth classic and low energy 100+ GPIO https://www.crowdsupply.com/krtkl/snickerdoodle Curious what other think about this one. Thanks, Chris
  9. arty $99 artix fpga board

    I too would like to see an artix papilio. What would design lab look like with Vivado vs the current ISE? I have been playing with the vivado on a zynq board. I think it would integrate nicely with designlab since the block designs already resemble the schematic design to me in ise. As to the point that keeps coming up with development boards about licensing and not open source. The point is these are for profit companies not charities. i would venture to say they are making money off the current licensing models and as long as they are then they will never make them opensource. That is just business and until some other company comes along to force them by open sourcing their tools I don't see it happening anytime soon.
  10. arty $99 artix fpga board

    Not sure if anyone saw this one yet. It is vivado based. Looks like a decent board. Looks like avnet and digilent are putting this one out. Nice to see one for less than $100 without requiring being student. www.xilinx.com/products/boards-and-kits/arty.html Any thoughts? Thanks, Chris
  11. Cubic Board FPGA

    James, I had seen discussions of the MIST board on other sites before also. For some reason I always thought it was a Xilinx Spartan board. Good to know. Thanks, Chris
  12. Cubic Board FPGA

    Jack, Yeah I saw that one too... They must have not looked too hard. Maybe they are referencing specific to Altera??? Thanks, Chris
  13. Cubic Board FPGA

    Not sure if anyone has seen this one yet http://cubicboard.org . It is an Altera board but I think it is a nice design. It is built by some Altera engineers, but not an Altera officially sanctioned project. I really like the way they separated the core board that you can use in your own designs from all the other boards. As I have mentioned before I like the core board/modular idea, which sounds like what the original papilio board was. It is open source also. It is like a parallella or other zynq board but has Altera fpga. I had sent an email to the project a while back about availability and heard back that I guess Terasic is reviewing it to possibly offer them for sale. Hopefully the price doesn't go way up over what they were originally targeting for price. I like that it is open source but looks to be well beyond my skills soldering the bga and all. Curious what others think about it and eventually what the pricing will be. Thanks, Chris
  14. VDHL signal module question

    Jack, Thanks for the info. Actually the controlReg0 and statusReg1 were not ports in the top level module, the only top level module port was the bus, which is why I didn't include in the top level port command I posted in the first message. So controlReg0 and statusReg1 were just signals defined in the top level module. They were used in the port command for the submodule though. That was what was so confusing about the code. It was much different than what I have seen how a lot of the wishbone vhdl code handles buses. The way I read it was that the bus is the only thing coming into the top level module. Then the bus and the registers are in the port to the sub module. It was like they designed the submodule to handle processing the registers. I think I will just build up a minimal test with a microblaze and try it out to see how it works and why they built it that way. Thanks to you and Alvie for the info, Chris
  15. VDHL signal module question

    Alvie, Sorry I had left them off for brevity. Yes controlReg0 is defined as signal std_logic_vector(31 downto 0) in the top level module and reg0 is defined as signal std_logic_vector(31 downto 0) in the submodule. Basically the register size of the 32 bit bus. The port is defined as OUT for reg0 and IN for reg1 on the submodule and I believe it is synchronous since both top level module and submodule processes are driven by the bus clock signal. I would post the whole code but it was pretty large with pages of other logic around processing on the bus signals and all. I was just trying to simplify the example to just the specific area I was interested in understanding. Any thoughts would be helpful. Thanks, Chris