stm

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Everything posted by stm

  1. Hi, my Papilio Duo has been put to rest for some years now, but now I want to reactivate it as a logic analyzer. But I forgot almost everything about how to use the Papilio Duo, and I can't find the current documentation. When I click on the "Learn" link at the top of the page, I only see an empty directory displayed by Apache. I've installed DesignLab 1.0.8 on Windows 10, and I can start the logic analyzer GUI from DesignLab, but the Papilio Duo does not show up as a serial port on the system. Where can I find the steps to get the Papilio Duo running again with my Windows 10 system? Thanks Stephan
  2. Ok, I found an old version of the "Learn" content in the Wayback Archive, maybe it helps others as well: https://web.archive.org/web/20170530173520/http://gadgetfactory.net/learn/ From there I found a video that helped me to reinstall the USB drivers in Windows 10: And now I am able to use the Papilio Duo as a logic analyzer again.
  3. Hi, I wonder how the access to the on-board RAM can be implemented and organized. So far I know that a ZPUino uses the on-board RAM to store programs and data. If I understand it correctly, the ZPUino implementation uses the sram_ctl8.vhd source to access the RAM chip via a Wishbone bus interface. I want to use the Papilio DUO to simulate an expansion board for an old 6502-based computer (Ohio Scientific Challenger 1P). On the one hand I want to use a part of the Papilio DUO RAM chip as a memory expansion for the 6502 board. On the other hand a floppy controller with attached floppy disks shall be simulated with storage on an SD card. So for the RAM expansion alone I only need to translate the 6502 bus to something that can communicate with the Papilio DUO's RAM chip. I either could create a Wishbone bus wrapper around the 6502 bus, and use the sram_ctl8.vhd as-is, or I could directly build a bridge from the 6502 bus to the RAM chip based on the internals of the sram_ctl8.vhd source. But when the floppy controller comes into the picture it gets more complicated. I need to simulate some of the chips for the floppy controller (6850 ACIA and 6820 PIA) and map them into the address space of the 6502. For access to an SD card I will either need to use a ZPUino or the real ATmega32U4 processor. With a ZPuino I would need to divide the RAM between the memory expansion and the ZPUino. So lots of questions arise: How can I divide the RAM between the ZPUino and other parts of my design? Could that be managed with compile and link time options when building the sketch for the ZPUino, or would I need to build something in VHDL? Is it even possible at all to influence the ZPUino's use of the RAM chip without modifying its implementation? Would it be better to use the ATmega32U4 for implementing the access to the SD card? I'm obviously at the very beginner level regarding designing and implementing such a project, so I would be very grateful about any tips and experiences in this area. Thanks Stephan
  4. Hi, I looked at the "Benchy_Sump_LogicAnalyzer" example. If I understand it correctly, the serial input/output of the "Sump Blaze Logic Analyzer x8" symbol goes to the ZPUino, and on the ZPUino there runs a sketch that forwards the serial IO to the serial port of the Papilio DUO board. Is it necessary to forward the data through the ZPUino, or can the logic analyzer be used in a design that doesn't have one? I tried to add the logic analyzer to a simple design of my own and connected the tx and rx pins of the logic analyzer to the TXD and RXD pins of the Pailio DUO. Then I tried to connect to it with Logic Analyzer GUI, but that didn't work so far. I tried device types "Original SUMP device" and "Papilio Logic Analyzer", and when I click "Show device metadata" I see the serial LEDs blinking on the Papilio board, but then the "Device type" is cleared and nothing is retrieved. And for my understanding who the logic analyzer works: I looked at the VHDL implementation of the logic analyzer, and I can't find any actual logic in there, just lots of mappings and constant definitions. Is this really the whole implementation, or are there additional modules involved that I was not able to find? Thanks Stephan
  5. Hi Alvie and Jack, this looks very interesting! Jack, I believe you mentioned before that this project would contain a DMA module. Is this already implemented? If so, could you point out where it is so I can take a look at it? Thanks Stephan
  6. stm

    Using on-board RAM in designs

    Magnus and Vlait, thanks for the suggestions. My idea was also that it would be the easiest way to use a zpuino-based solution, with a FAT file system on the SD card. I will a look at the Pipistrello solution.
  7. stm

    Using on-board RAM in designs

    Yes, this requires clock domain crossing. The 6502 runs at 1 MHz.
  8. stm

    Using on-board RAM in designs

    I don't have any design yet, except my own previous tries to implement the DMA Wishbone peripheral where only the read cycle works (see earlier posts in this thread). The 6502 has a clock frequency of 1 MHz, so an upper bound is 1 million bytes per second, but in practice will be probably less than 500000 bytes per second as the 6502 cannot read/write on every clock cycle.
  9. stm

    Using on-board RAM in designs

    Hello Alvie, my project is a RAM expansion and floppy emulator for a 6502 board, and this means read/write random access at byte level. Do you mean a cache in connection with your burst controller? Stephan
  10. stm

    Using on-board RAM in designs

    Thank you, Jack! Please let me know when something is available. In the meantime I will try to make progress with Alvie's proposal. Stephan
  11. stm

    Using on-board RAM in designs

    Thanks Alvie, I will take a look. I only need read and write for a single byte at a time, but probably this can be tailored to my needs. Stephan
  12. stm

    Using on-board RAM in designs

    Hello Jack, I'm currently trying to revive my Papilio Duo project that I abandoned earlier this year. I still have no luck with my own DMA implementation, I can't make it work.Therefore I wanted to ask whether you actually did implement a Wishbone peripheral for SDRAM access, as you outlined in your post. Did anything happen in this area, or are you still planning to do this? Stephan
  13. Hi, after a long pause I'm coming back to hack on my Papilio Duo, and of course I updated to the current DesignLab 1.0.7. Now I feel like a complete newbie :-) After clicking "New ZPUino SOC project" I get a new editor, but "Save as..." is disabled, and I cannot edit the sketch. When I click "Edit circuit", it tells me that there are readonly files, and then can I save the project to a new location. But after that it is still not possible to edit the sketch, What am I doing wrong. And also a general question: What is the correct way to upgrade from one DesignLab version to the next one? If I open an existing project and do "Edit Circuit", I get lots of messages about duplicate references, because there are still references to the old DesignLab directory. -- Stephan
  14. Nevermind, it was in fact my own fault because I had switched on "Use external editor" in the preferences...
  15. I tried with different projects now, and DesignLab 1.0.7 does not let me edit any C source of any of my projects.
  16. Hi Jack, thanks, the messages about the duplicate references are gone after uninstalling the old instance of DesignLab. But maybe I didn't make my other problem clear: Xilinx ISE was and is installed, and it opens fine from within DesignLab 1.7. What does not work is editing the C code of the sketch itself in the DesignLab Arduino IDE (see attached screen shot). The editor window is readonly, and it doesn't allow me to edit the code. Stephan
  17. stm

    Using on-board RAM in designs

    That sounds easy, therefore good :-) For the memory expansion aspect of my project this will be fine. You might recall that exposing a part of the Papilio RAM as a memory expansion for a 6502-based computer is the first step of my project. The second step will be to use the Papilio DUO also as a floppy disk emulator with storage on an SD card. This will also need a buffer in RAM. I guess that I will then have to manage a larger chunk of memory and use part of the memory as memory expansion and another part as disk buffer. Stephan
  18. stm

    Using on-board RAM in designs

    Hello Jack, it would be very helpful if you could put up a working DMA example! The implementation of such a thing apparently is a little bit hard for a VHDL newbie like me... Please let me know if can help in any way, maybe with testing. I have the prototype of my DMA peripheral on GitHub, maybe I'm doing something obviously stupid: The classic implementation with the wb_master_np_to_slave_p.vhd wrapper is on the master branch: https://github.com/smuehlst/c1p610/tree/master/memext My last attempt to implement the pipeline cycle is on the "feature_pipeline" branch: https://github.com/smuehlst/c1p610/tree/feature_pipeline/memext Thanks Stephan
  19. stm

    Using on-board RAM in designs

    It seems like I'm trying to go where no man has gone before in Papilio land... Jack, you mention in the thread Hardware Verification for AVR8 Soft Core a tool to generate a ROM image for simulating an entire AVR8 soft processor in Xilinx ISE. Would that be usable also for simulating the whole ZPUino in ISE? It looks that this is the only option for me to find the problem with my DMA peripheral. How would one set up the actual RAM in such a simulation?
  20. stm

    Using on-board RAM in designs

    I've stil made no progress with the DMA peripheral implementation, so I need again to ask for help. As I'm not able to get the peripheral to work with the wb_master_np_to_slave_p.vhd wrapper around my "classic standard single read/write cycles" implementation, I'm now trying to implement the "pipelined read/write cycle" directly. For that I have a question about the significance of the Wishbone STALL_I signal of the DMA master. Alvie wrote earlier that I need to take that signal into account. But if I understand the Wishbone specification correctly, this is only relevant if the master tries to make multiple read/write cycles in a row, and if the slave wants to signal that it can't take further requests. My current implementation will only do a single read or write. So it will start a read or write cycle and then wait for the high ACK_I signal from the slave. Am I correct that in this scenario the STALL_I signal can be ignored, and that the master can simply wait for the ACK_I signal from the slave?
  21. stm

    Using on-board RAM in designs

    Hi Alvie, sorry for being such a pain, but were you able to look into the problem? What can I do myself to further troubleshoot the issue? Thanks Stephan
  22. stm

    Using on-board RAM in designs

    Yes, I'm using the wb_master_np_to_slave_p.vhd wrapper.
  23. stm

    Using on-board RAM in designs

    Hello Alvie, I now added a read and a write cycle with stalling to the ISim simulation (see attached image). The cycles that include stalling are a write cycle that starts at 220ns and a read cycle that starts at 340ns. Do these look correct? Stephan
  24. stm

    Using on-board RAM in designs

    You are right, my simulation does not model stalling, and I'm not using a RAM model in the simulation. I was not aware that one is available, or do you mean the sram_ctl8.vhd module? My VHDL testbench simply sets ACK_I after a cycle to acknowledge the read or write. I will try to model stalling in the simulation to see how it behaves. As we found out earlier my initial implementation of the DMA peripheral was non-pipelined. It implemented the "classic standard single read/write cycles". After your hint I added the wb_master_np_to_slave_p.vhd wrapper around it, and that is what you are seeing in the simulation above. When I added the wrapper, the read cycle started to work. I was under the impression that the wb_master_np_to_slave_p.vhd wrapper would deal with stalling. I will send you my current implementation and the test bench, thanks for taking a look! Stephan
  25. stm

    Using on-board RAM in designs

    Hello Alvie, if you mean the diagram of an ISim simulation, I have attached a picture when running the DMA peripheral in an ISim simulation. The s_* signals are the signals connected to the "wishbone_slot_video_out" and "wishbone_slot_video_in" buses in the full circuit with the ZPUino. The DMA write cycle starts at 170ns and the DMA read cycle starts at 220ns. Stephan