stm
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Wishbone version of the Sump Blaze Logic Analyzer
stm replied to Jack Gassett's topic in DesignLab Libraries
Hi Alvie and Jack, this looks very interesting! Jack, I believe you mentioned before that this project would contain a DMA module. Is this already implemented? If so, could you point out where it is so I can take a look at it? Thanks Stephan -
Magnus and Vlait, thanks for the suggestions. My idea was also that it would be the easiest way to use a zpuino-based solution, with a FAT file system on the SD card. I will a look at the Pipistrello solution.
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Yes, this requires clock domain crossing. The 6502 runs at 1 MHz.
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I don't have any design yet, except my own previous tries to implement the DMA Wishbone peripheral where only the read cycle works (see earlier posts in this thread). The 6502 has a clock frequency of 1 MHz, so an upper bound is 1 million bytes per second, but in practice will be probably less than 500000 bytes per second as the 6502 cannot read/write on every clock cycle.
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Hello Alvie, my project is a RAM expansion and floppy emulator for a 6502 board, and this means read/write random access at byte level. Do you mean a cache in connection with your burst controller? Stephan
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Thank you, Jack! Please let me know when something is available. In the meantime I will try to make progress with Alvie's proposal. Stephan
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Thanks Alvie, I will take a look. I only need read and write for a single byte at a time, but probably this can be tailored to my needs. Stephan
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Hello Jack, I'm currently trying to revive my Papilio Duo project that I abandoned earlier this year. I still have no luck with my own DMA implementation, I can't make it work.Therefore I wanted to ask whether you actually did implement a Wishbone peripheral for SDRAM access, as you outlined in your post. Did anything happen in this area, or are you still planning to do this? Stephan
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Nevermind, it was in fact my own fault because I had switched on "Use external editor" in the preferences...
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I tried with different projects now, and DesignLab 1.0.7 does not let me edit any C source of any of my projects.
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Hi Jack, thanks, the messages about the duplicate references are gone after uninstalling the old instance of DesignLab. But maybe I didn't make my other problem clear: Xilinx ISE was and is installed, and it opens fine from within DesignLab 1.7. What does not work is editing the C code of the sketch itself in the DesignLab Arduino IDE (see attached screen shot). The editor window is readonly, and it doesn't allow me to edit the code. Stephan
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Hi, after a long pause I'm coming back to hack on my Papilio Duo, and of course I updated to the current DesignLab 1.0.7. Now I feel like a complete newbie :-) After clicking "New ZPUino SOC project" I get a new editor, but "Save as..." is disabled, and I cannot edit the sketch. When I click "Edit circuit", it tells me that there are readonly files, and then can I save the project to a new location. But after that it is still not possible to edit the sketch, What am I doing wrong. And also a general question: What is the correct way to upgrade from one DesignLab version to the next one? If I open an existing project and do "Edit Circuit", I get lots of messages about duplicate references, because there are still references to the old DesignLab directory. -- Stephan
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That sounds easy, therefore good :-) For the memory expansion aspect of my project this will be fine. You might recall that exposing a part of the Papilio RAM as a memory expansion for a 6502-based computer is the first step of my project. The second step will be to use the Papilio DUO also as a floppy disk emulator with storage on an SD card. This will also need a buffer in RAM. I guess that I will then have to manage a larger chunk of memory and use part of the memory as memory expansion and another part as disk buffer. Stephan
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Hello Jack, it would be very helpful if you could put up a working DMA example! The implementation of such a thing apparently is a little bit hard for a VHDL newbie like me... Please let me know if can help in any way, maybe with testing. I have the prototype of my DMA peripheral on GitHub, maybe I'm doing something obviously stupid: The classic implementation with the wb_master_np_to_slave_p.vhd wrapper is on the master branch: https://github.com/smuehlst/c1p610/tree/master/memext My last attempt to implement the pipeline cycle is on the "feature_pipeline" branch: https://github.com/smuehlst/c1p610/tree/feature_pipeline/memext Thanks Stephan
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It seems like I'm trying to go where no man has gone before in Papilio land... Jack, you mention in the thread Hardware Verification for AVR8 Soft Core a tool to generate a ROM image for simulating an entire AVR8 soft processor in Xilinx ISE. Would that be usable also for simulating the whole ZPUino in ISE? It looks that this is the only option for me to find the problem with my DMA peripheral. How would one set up the actual RAM in such a simulation?