quicky

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About quicky

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  1. quicky

    USB Issue on AVR side.

    I answer to myself. I just reload the Design using papilio-prog and it is fine. I also observe that some time the devttyUSB port doesn`t change between the burn of bootloader and the upload of AVR sketch but I don`t know why...
  2. quicky

    ftdi_user.sh issue on Kubuntu 64 bits

    Corresponding github issue is the following : https://github.com/GadgetFactory/DesignLab/issues/10
  3. quicky

    Compilation of Basic Arduino Sketch failed

    Issue created on DesignLab Github https://github.com/GadgetFactory/DesignLab/issues/19
  4. Issue created https://github.com/GadgetFactory/DesignLab/issues/18
  5. Yes this is exact what I planned to make your life easier
  6. Hi Jack, When trying to restore the AVR bootloader I obtain an error message because file DesignLab-1.0.x/hardware/arduino/avr/bootloaders/caterina/Caterina-Papilio-duo.hex do not exist. The correct file seems to be DesignLab-1.0.x/hardware/arduino/avr/bootloaders/caterina/Caterina-Papilio-DUO.hex Coudl you perform the necessary corrections in DesignLab so that it searchs the correct name ?
  7. quicky

    USB Issue on AVR side.

    To try to advance I retry the solution to program the AVR through FPGA as I cannot program AVR directly. As DesignLab is calling the papilio-prog.exe which is a Windows executable I replace it by a symbolic link on DesignLab-1.0.1/hardware/tools/papilio/lin64/papilio-prog and then I try to reprogram through FPGA. At this time serial Port is /dev/ttyUSB0 it seems the load of bitstream succeed : Binary sketch size: 4,830 bytes (of a 32,768 byte maximum) - 14% used/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe -f /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/arduino/avr/bootloaders/caterina/Papilio_DUO_ArduinoISP.bit Using built-in device listJTAG chainpos: 0 Device IDCODE = 0x24001093 Desc: XC6SLX9Created from NCD file: top_avr_core_v8.ncd;UserID=0xFFFFFFFFTarget device: 6slx9tqg144Created: 2014/09/08 22:13:31Bitstream length: 2724832 bitsUploading "/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/arduino/avr/bootloaders/caterina/Papilio_DUO_ArduinoISP.bit". DNA is 0xd9fc033c4f083ffe/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avrdude -C/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avrdude.conf -q -q -patmega32u4 -cstk500v1 -P/dev/ttyUSB0 -b57600 -Uflash:w:/tmp/build3775892055425291095.tmp/tutu.cpp.hex:i -Ulock:w:0x2F:m avrdude: ser_open(): can't open device "/dev/ttyUSB0": No such file or directorybut the serial port is no more the same when trying to upload the sketch. I reuse the avrdude command by replacing the serial port by the new One and now it seems that he sketch upload was successfull In your opinion is it normal that the serialPort change ? The remining issue is now that I no more have a design on my FPGA. Is there a way to restablish it automatically after the load of Arduino sketch ?
  8. quicky

    USB Issue on AVR side.

    Hi, My coworker who has also the Papilio Duo has exactly the same issue when trying to load a firmware on the AVR When searching for avrdude error message on Internet I find a lot of Arduino topics where users had exactly the same issues ( avrdude: error: buffered memory access not supported. Maybe it isn't a butterfly/AVR109 but a AVR910 device? ) but it seems there is no magical solution to solve it..
  9. Hi Jack, I just downloaded DesignLab-1.0.3 and tried to compile a simple sketch ( Arduino basic blink LED) in order to test upload to AVR side but there is an issue inside DesignLab at the end of compilation: Sketch uses 4,732 bytes (16%) of program storage space. Maximum is 28,672 bytes.Global variables use 42 bytes (1%) of dynamic memory, leaving 2,518 bytes for local variables. Maximum is 2,560 bytes.java.lang.NumberFormatException: null at java.lang.Integer.parseInt(Integer.java:454) at java.lang.Integer.parseInt(Integer.java:527) at processing.app.Sketch.size(Sketch.java:1721) at processing.app.Sketch.build(Sketch.java:1604) at processing.app.Sketch.exportApplet(Sketch.java:1625) at processing.app.Sketch.exportApplet(Sketch.java:1611) at processing.app.Editor$DefaultExportHandler.run(Editor.java:2666) at java.lang.Thread.run(Thread.java:745)
  10. quicky

    USB Issue on AVR side.

    Hi Jack, I just dowload DesignLab 1.0.3 for linux64. I ran ftdi_user script successfully ( with the patches to make it really suitable for 64 bits Ubuntu) but the other points the result is worse compared to DesignLab-1.0.1 ! Now it is no more possible to compile the AVR sketch, there is a java exception ! I copy paste below the result obtained when trying to compile the example Arduno basics Blink : Sketch uses 4,732 bytes (16%) of program storage space. Maximum is 28,672 bytes.Global variables use 42 bytes (1%) of dynamic memory, leaving 2,518 bytes for local variables. Maximum is 2,560 bytes.java.lang.NumberFormatException: null at java.lang.Integer.parseInt(Integer.java:454) at java.lang.Integer.parseInt(Integer.java:527) at processing.app.Sketch.size(Sketch.java:1721) at processing.app.Sketch.build(Sketch.java:1604) at processing.app.Sketch.exportApplet(Sketch.java:1625) at processing.app.Sketch.exportApplet(Sketch.java:1611) at processing.app.Editor$DefaultExportHandler.run(Editor.java:2666) at java.lang.Thread.run(Thread.java:745)To avoid these java/DesignLab issues and concentrate to upload of firmware to AVR could you indicate me precisely a set of command line to execute outside of DesignLab to try to manually upload the firmware to AVR ?
  11. quicky

    ftdi_user.sh issue on Kubuntu 64 bits

    Hi Jack, I just download DesignLab 1.0.3 for Linux64 and look at ftdi_user script and it seems that the problem I reported about this topic has not been solved. The scrip still refer to 32bits version of papilio-prog
  12. quicky

    USB Issue on AVR side.

    Hi Jack, I will try it in few hours. For DesignLab 1.0.1 I had to patch ftdi_user script but due to 64bits instead of 32 bits.The only differences between Kubuntu and Ubutuntu are related to Desktop manager... The ftdi_user script is related to FPGA serial port only or it should also concern AVR serial port ? because the udev rule files generated by this script contains only USB Vendor and Devices Ids that I observe when pluggin FPGA USB side so I`m not to sure to understand why you mention ftdi_user script for AVR USB issue
  13. quicky

    USB Issue on AVR side.

    Hi Jack, Sorry to reopen this thread but I also have issues with AVR side of my Papilio Duo. I`m using Kububtu 14,04 LTS and try to follow the tutorial for AVR side but the upload to the board fails. The serial port of AVR is /dev/ttyACM0 for me. When I select it and ask for Upload I obtain the following ( in DesignLab preferences verbosity checkbox are checked for both Compilation and Upload ) /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avr/bin/avr-objcopy -O ihex -R .eeprom /tmp/build8484831947675701476.tmp/tutu.cpp.elf /tmp/build8484831947675701476.tmp/tutu.cpp.hex Executing /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avr/bin/avr-size -A /tmp/build8484831947675701476.tmp/tutu.cpp.hexBinary sketch size: 4,830 bytes (of a 28,672 byte maximum) - 16% usedForcing reset using 1200bps open/close on port /dev/ttyACM0PORTS {/dev/ttyACM0, /dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyS0, } => {}processing.app.debug.RunnerException: Couldn't find a Board on the selected port. Check that you have the correct port selected. If it is correct, try pressing the board's reset button after initiating the upload. at processing.app.debug.BasicUploader.waitForUploadPort(BasicUploader.java:266) at processing.app.debug.BasicUploader.uploadUsingPreferences(BasicUploader.java:97) at processing.app.Sketch.upload(Sketch.java:1681) at processing.app.Sketch.exportApplet(Sketch.java:1623) at processing.app.Sketch.exportApplet(Sketch.java:1595) at processing.app.Editor$DefaultExportHandler.run(Editor.java:2673) at java.lang.Thread.run(Thread.java:745)I also tried to run DesignLab as root to check if there were any differences and I obtain the following : /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avr/bin/avr-gcc -Os -Wl,--gc-sections -mmcu=atmega32u4 -o /tmp/build5258795649659095730.tmp/tutu.cpp.elf /tmp/build5258795649659095730.tmp/tutu.cpp.o /tmp/build5258795649659095730.tmp/core.a -L/tmp/build5258795649659095730.tmp -lm /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avr/bin/avr-objcopy -O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0 /tmp/build5258795649659095730.tmp/tutu.cpp.elf /tmp/build5258795649659095730.tmp/tutu.cpp.eep /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avr/bin/avr-objcopy -O ihex -R .eeprom /tmp/build5258795649659095730.tmp/tutu.cpp.elf /tmp/build5258795649659095730.tmp/tutu.cpp.hex Executing /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avr/bin/avr-size -A /tmp/build5258795649659095730.tmp/tutu.cpp.hexBinary sketch size: 4,830 bytes (of a 28,672 byte maximum) - 16% usedForcing reset using 1200bps open/close on port /dev/ttyACM0PORTS {/dev/ttyACM0, /dev/ttyS0, } / {/dev/ttyS0, } => {}PORTS {/dev/ttyS0, } / {/dev/ttyACM0, /dev/ttyS0, } => {/dev/ttyACM0, }Found upload port: /dev/ttyACM0/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avrdude -C/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avrdude.conf -q -q -patmega32u4 -cavr109 -P/dev/ttyACM0 -b57600 -D -Uflash:w:/tmp/build5258795649659095730.tmp/tutu.cpp.hex:i Connecting to programmer: .Although the result seems to be better the upload never terminate I tried to directly launch the avrdude command in a terminal ( both as root and normal user ) and I obtain the following message : /media/LaCie/synchronized/Rack/Programmation/fpga$ sudo /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avrdude -C/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/avrdude.conf -q -q -patmega32u4 -cavr109 -P/dev/ttyACM0 -b57600 -D -Uflash:w:/tmp/build5258795649659095730.tmp/tutu.cpp.hex:iConnecting to programmer: .Found programmer: Id = "Papilio"; type = l Software Version = P.a; Hardware Version = p.iavrdude: error: buffered memory access not supported. Maybe it isn'ta butterfly/AVR109 but a AVR910 device?but I don`t know what to conclude from that I also tried to use the AVR programming through FPGA but DesignLab generate the following error message : /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe -f /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/arduino/avr/bootloaders/caterina/Papilio_DUO_ArduinoISP.bit /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe: 1: /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe: MZ%G����%@@%G���%@: not found/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe: 2: /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe: Syntax error: ")" unexpectedBy looking closer it seems that papilio-prog.exe is the windows Papilio Loader which I don`t understand being under Kubuntu and unfortunately I don`t know how to make DesignLab use the Linux version of Papilio Load In desperation I tried the tutorial AVR side part that describe how to restore the booloader but DesignLab generate the same error message than when trying to use FPGA to load the sketch on AVR: /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe -f /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/arduino/avr/bootloaders/caterina/Papilio_DUO_ArduinoISP.bit /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe: 1: /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe: MZ%G����%@@%G���%@: not found/media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe: 2: /media/LaCie/synchronized/Rack/Programmation/fpga/DesignLab-1.0.1/hardware/tools/papilio/papilio_loader/bin/papilio-prog.exe: Syntax error: ")" unexpectedI`m completely lost and desperate. I don`t know how to debug that... Any ideas ? For information the load of FPGA circuit works properly, I succeed to migrate one of my VHDL design from Papilio One 500k on Papilio Duo successfully Thnaks by advance for your help
  14. quicky

    Using PapilioLoader on Papilio DUo

    Good news ! I will try to test it these evenings or tomorrow
  15. quicky

    ftdi_user.sh issue on Kubuntu 64 bits

    I just talk about the fact that papilio-prog is located here ( hardware/tools/papilio/lin32/papilio-prog ) and here (tools/Papilio_Loader/programmer/linux32/papilio-prog) The fact there is a 32 bits package and a 64 bits package of DesignLab is fine for me. Hope this make things more clear