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About papry

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  1. Spotted something on Ebay UK and though others might be interested. "Papilio Pro FPGA with Arcade Megawing (Xilinx Spartan 6)" but it now @ £64.99. Seems good value to me. Note: I have absolutely no connection with the seller. Out of interest I searched for "Papilio FPGA" on Amazon UK. "SeeedStudio Papilio Duo-2Mb Fpga On The Top Atmega32U4 On The Botom DIY Maker Open Source BOOOLE" @ £188 ($245). Ouch! "Papilio Duo-2Mb" @ £201 ($262). ...and various other overpriced Papilio related boards.
  2. papry

    Changing the clock frequency

    Just a quick comment that to generate a slower clock, a preferred method is to use a synchronous counter. This type of counter has all counter flops clocked by the same high speed input clock and fits well with the way that FPGAs handle clocks. It is also the way that this type of circuit would be designed in an ASIC. Here is some code I wrote recently (as an example). It divides 315MHz from a PLL to 3.57MHz. A divide by 88 is required. reg [6:0] pll315_counter; reg clk357; // create 3.57MHz NTSC clock by dividing 315MHz by 88 always @ (posedge w_clk315) begin clk357 <= (pll315_counter<7'd44); if (pll315_counter==7'd87) begin pll315_counter <= 7'b0; end else begin pll315_counter <= pll315_counter + 7'b1; end end You would need to change the counter length, termination count and half count to suit your frequencies. I should have really used constants (such as tick defines) rather than hard code numbers, but hey this is my personal hobby project 😃
  3. I have a number of FPGA boards, including several Papilios, and recently acquired a Digilent Artix 7 CMOD A7. The nice thing about this board is the form factor (can plug into a breadboard), and the inclusion of a large SRAM (not SDRAM!). I found a number of projects on Hamsters web pages (excellent learning material BTW), specifically a project to use this board to output 1080p over a HDMI cable. I have spent the past few evenings converting the VHDL code into Verilog. It's not that difficult. I think that I have spotted a bug where the constant 720 is used instead of 1080 (the video is 1080p, but perhaps the code was original for 720p?). I have brought hsync and vsync out to pins in order to check timings on a scope (that's how I found the bug). I was puzzled as to why I was seeing no signals whatsoever on the high-speed TDMS differential pins, until I finally realised that they need 50ohm pull-ups to +3.3V. This is normally done at the other end of the HDMI cable, but I don't have one currently connected. I popped in some resistors and finally saw some waveforms on the differential pins. They were pretty nasty. I really need a scope with much higher bw! Just today I got a HDMI breakout board, ordered from Ebay. I will now be able to connect a HDMI cable to a monitor. To get started I really want to drop down the timings from 1080p to 576p (UK 50Hz standard definition), but I can't find the pixel numbers for the vsync, front/back porch etc. If anyone has a definitive list, please let me know! I can compile for either 1080p or 640x480 VGA timings (no idea if this will be recognised over HDMI). At 1080p I am failing timing analysis. This is where I struggle. I am using a PLL to boost the 12MHz xtal to the 100MHz needed by the original code. I am trying to define in the XDC the clocks. I know how to define the XTAL clock, but I am having problems telling Vivado about the internal clocks. In fact I am not sure whether I really need to or whether it can infer the clocks from the MCM parameters? I tried using the timinng constraints wizard, but it wanted to add constraints for the TMDS outputs, but I had no idea what numbers to use. Any guidance from anyone who has played with HDMI would be greatly appreciated. Once I have something (low res) working with the CMOD-A7 I will go back to the Papilio Pro and get something working here.
  4. papry

    VGA Wing (6 bit)

    OK Dave. I am not a prolific poster, but it did pass my mind to post some pictures once the project had developed. BTW I do have a habit of not finishing things off. If it is Papilio specific I will post here, otherwise I will post to Stardot (where I am user acory). --Gary
  5. papry

    Why 32MHz XTAL?

    Excellent idea! Like all good ideas they are simple and obvious (in hindsight)! I need 65MHz, but I can see several ways to get there with 2 DCM_SPs. Many thanks Alvieboy.
  6. papry

    VGA Wing (6 bit)

    Ah! OK. It is not a problem. I probably can get someone at work to replace the resistors. BTW I am in the UK. The MC6847 chip which I am trying to emulate, only supported limited colours anyway. The project is part of emulating an old UK 6502 "Acorn Atom" computer. Someone has already done an excellent full port of this computer to the Papilio (known as Hoglet on the BBC/Acorn forum, and on this forum too). For me it is simply a for fun and learning project. I will connect the Papilio One to a real (3.3V) 65C02, and 64k bytes RAM, rather than emulate them in the FPGA. The only problem is that I will probably run out of FPGA pins (16 needed for the address and 8 for the databus, leaving only 8 for other 65C02 and RAM pins). The idea was to connect to a real (old) X,Y matrix keyboard which I have, but this could be a problem :-). I guess I might have to wait for the Papilio Pro Plus to be released which hopefully will have far more pins!
  7. papry

    VGA Wing (6 bit)

    Sorry if I wasn't clear. All 3 VGA colour analogue inputs connect to 2 FPGA pins via resistors of the exact same value (marked 271 - using a magnifying glass). I was expecting one resistor to be half the value of the other. So code 00 is black, code 11 is full intensity (luminance), but codes 10 and 01 result in the same luminance. On the bottom is appears to be make by Sparkfun. On the MegaWing there are 3 resistors for the red and green channels (2k, 1k and 510 ohms). They form a potential divider with the 75 input impedance of the monitor. On the Altera board there are 5 resistors per channel (similarly 500, 1k, 2k, 4k and 8k ohms). I made a project which simply ramped the count from 0 to 31 and viewed the voltage on a scope. I was surprised to see that code 15 (01111 binary) was at a higher voltage than code 16 (10000 binary). In this simple scheme I suspect that the output impedance of the FPGA driver has not been taken into account, and has an impact. I tried different drive strengths and the ramp steps did change in the area of the 15 to 16 transition.
  8. papry

    Why 32MHz XTAL?

    I am sure that there are many cases of people wondering "why did they use that part", and the answer is simply, when they made the design, that part was simply the part that was on hand. I am pretty familiar with PLLs and the like, and in the case of the DCM_SP with a 32MHz reference, 65MHz is simply not possible. I checked Mouser and replacement xtal osc modules are around £1, so I will likely go this route.
  9. papry

    Contradiction in description

    It's a pity that the FTDI programmer can't be disconnected from the JTAG pins of the FPGA. I was given an old Xilinx FPGA board with the 1mm pitch header, but I was unable to do anything with it, because I didn't have a Xilinx programmer. At least in the UK on Ebay these are quite expensive. There are Altera programmers on Ebay and they are very cheap indeed. I searched for a FDTI 2232 board on Ebay, but suprisingly they are quite rare (although I did spot one for $10 in Hong Kong). If a new Papilio board is ever made, it would be a great feature (for some people at least) if there was a way to use the programmer stand-alone.
  10. papry

    Why 32MHz XTAL?

    Last night I ported some VGA type Verilog code from an Altera board to my Papilio One. I needed to generate a 65MHz internal clock, but was surprised at the lack of flexibility of the DCM_SP clock generator. I was able to relatively simply generate 64MHz, which was good enough and my old Dell VGA monitor synced correctly, however some of the clock phase controls needed to be tweaked. It occured to me that it might have been better to use a lower frequency reference crystal, such as 10MHz (or even lower if the DCM allows), as it would give more flexibility. I do of course realise that some frequencies will be impossible whatever the reference XTAL. Purely out of curiosity, I wondered why a frequency of 32MHz was selected? I also tried out adding a PLL to my blink Papilio Pro project, and found the same issue. 65MHz was not possible (only 64 or 66MHz). I checked the Altera project and the PLL was more flexible in that 65MHz was possible. I have seen some FPGA dev boards which use a programmable frequency chip, rather than a crystal and I can now see why that might be a really useful feature.
  11. papry

    VGA Wing (6 bit)

    Last night I ported my unfinished MC6847 emulator Verilog code from a Altera EPC4 board to my Papilio One. I have the small VGA wing, which has: hsync; vsync; and 2 bits each for R, G and B. When I found the schematic I was surprised to see that both resistors were the same value, which I believe will only allow my 3 levels of luminance for each colour, so only 27 colours in total. Why not use two different values for the resistors, similar to the scheme used on the other MegaWings? To be honest it isn't an issue for this particular project. I know that I could replace one of the resistors, but I am unable to work with that tiny size of SMD resistor.
  12. papry

    Papilio Pro still produced?

    I wonder how many users of this board are frightened or put off using the SDRAM due to the complexity? I am! I have read the datasheet, and I was surprised that this device is a lot more complicated than an old fashioned 64kbit DRAM which at least only needed the refresh. I was tempted by the Duo, mainly because of the use of the Static RAM, but the cost in the UK (from SKPang) has risen enough to put me off. I will be in the US in May, so perhaps I could order one and have it delivered to the hotel??? For my current project (which is stalled somewhat) I am using all the I/O for DAC and ADC connections, leaving no spare pins to wire up a simple DIL SRAM, or even the VGA adapter. I guess I was wondering how many people bought the Pro and then didn't ever use the SDRAM. Given that you possible have to re-work the board to take a different SDRAM, could you make connections for SDRAM on the top layer and SRAM on the bottom layer, allowing you to offer a Pro+ with either SDRAM mounted or SRAM mounted. Just wondering... Anyway Jack, thanks for a great product.
  13. Hi keesj, in case you are monitoring this thread (or get an alert). On Ebay UK at the moment (23-Nov-2017) there is a Papilio set for sale "Papilio Pro Spartan 6 LX9 FPGA + 2 Mega Wing". It is £70 "buy it now". It has been there for a few days. Description in bold. Selling a Papilio Pro FPGA, perfect to learn FPGA with 2 megawing. Papilio Pro - Spartan 6 LX9 FPGA / 64Mbit SDRAM Papilio LogicStart MegaWing Papilio Arcade MegaWing I am not the seller, nor do I have any connection. As usual, let the buyer beware. regards... --Gary P.S. I hate this editor! It seems to insert a paragraph when I hit return. It's just as irratating as the default email behaviour in Thunderbird.
  14. I have used SK Pang Electronics ( which is a company based in the UK. I just checked and they have the Papilio Pro and Duo in stock. They are out of stock of other items. I noticed that prices rose significantly around the time of the Brexit result, and the fall of the UK pound against the dollar and other currencies. Then again you will get a better rate with the euro against the pound, which will offset for you. Buy now while the UK is still in the EU :-) good luck... --Gary
  15. Well this looks like the right thread to ask my question, rather than open a new one. Hopefully people will notice the new posting! I have been given a Spartan 3 based tiny PCB. It has a large SRAM, Flash ROM, 32 pin general purpose header, and a few switches and LEDs. It also has a 14 way header (smaller than 0.1") which I am told is for a standard Xilinx programmer. Well I don't have a Xilinx programmer, although I do have a cheap Chinese Altera programmer. So I wondered if I could use the programming circuitry on my Papilio One/Pro (I believe they are the same). The Papilio programmer appears to be based around the FTDI2232, a dual channel USB to UART. I am guessing that it is not used in serial "RS232" mode, but the JTAG pins are toggled high and low. Given that I cannot isolate the JTAG pins (TCK, TMS, TDI and TDO), the answer must be no. Interestingly there does appear a row of empty vias for soldering in a header for an external programmer, but I can't tap off from this as there would be contention on the TDO connection. Now I have a Sparkfun FDTI breakout board, but when I found it, it uses the single channel FDTI232R chip and not the dual channel chip. I have access to all pins. The question is, will this work with the Papilio Loader? Well I tried it out. Using simple COMMs software it works correctly as COM5 if I connect TX and RX. When I start the Papilio Loader, I get no messages to confirm that any programmer has been seen, nevertheless I loaded a random bit file and hit the "Run" button. For a few seconds the TX/RX (still linked together) light up, and then go out. The "Run" button is still greyed out. So is the Papilio Loader really using this single channel chip as a programmer? If there are multiple FDTI chips plugged into the USB, including a Papilio, how does the software figure out which to use? Note: I am using Papilio Loader 2.6. I think the latest version is 2.8, which I ought to try out. --Gary