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papry last won the day on March 25 2021

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  1. papry

    Where's Jack?

    Hi Ben, yes the Papilio boards are a great choice. One of these boards was my very first FPGA board, and I have had lots of fun and frustration. Iniitially using the Papilio One didn't go well, but I managed to work through the various problems and finally was able to start writing my own code. Still no idea what has happened to jack :-(
  2. Apologies as this is obviously somewhat off topic (different hardware). Previously I have compiled the VHDL source of the SUMP code for the Papilio One and successfully used it with the 5V level translater wings. This solution is incredible value, as even 8 or 16 bit logic "hobbiest" logic analysers cost many hundreds of dollars. Recently I bought a cheap FPGA board called the RV901T from China. I has 64 I/Os at 5V level (grouped into banks of 32). There are some direct FPGA connections too. However a stand alone Xilinx programmer is required and soldering skills to wire up the JTAG pins. The board has a Xilinx Spartan6 (like the Papilio Pro) but bigger (XC6SLX16). The original article was on Hackaday. So I started to write Verilog code to check that each pin toggled and that the direct FPGA pins could support serial comms using my own UART code. Good job I checked because I did need to remove a pull down resistor pack. Having got this far I decided to try to code my own logic analyser to be compatible with the OLD protocol and software. After a few bugs have been fixed from the LogicSniffer GUI I can get it to read the meta data. Question - can the device string be anything or for it to work does the software expect certain strings (device types)? Question - does anyone have a larger dump of all transactions over the serial comm port? Reason is I think the OLS protocol is not completely documented. Although the GUI sees the meta data it doesn't appear to ask for a capture. Perhaps it doesn't recognise my device "RV901T"? Any answers would be much appreciated. I intend to put the completed code on Github for others to use. BTW I was aware of the Pipistrello Verilog code which was helpfully posted in a earlier posting in this forum section. I have taken a look, but found the code hard to read.
  3. papry

    Where's Jack?

    Nice to see that all the spam postings have been removed/cleaned up. My question is the same, where is Jack Gassett?
  4. papry


    I've tried a couple of fairly simple things to try to eliminate possible reasons for the audio problems. I wired up a 8 bit Ferranti ZN428 (really old chip now, but easy to use) to 4 spare outputs in order to check the datastream without the sigma-delta DAC. The audio was distorted in an identical way. I then added a second Pokey (easy with RTL and a FPGA!) and wrote some simple code to write test values to it, in fact the same ones as listed in the schematics. The tones were generated correctly. In amongst all the noise, there is some hint of correlation with what is happening on the screen. I'm not sure what to try next :-(. I'll post again if I make any progress.
  5. papry

    Hamsterwoks dead??

    Yes it is dead. I posted a tweet and got quite a few replies including one from Mike Field confirming that the website was down. The reason is that he was getting a lot of requests for support with respect to the code on this site and he felt that having put the effort in to help got little thanks in return. You can still access the site via the "wayback machine". I found a python tool to scrape the site from the Wayback site, so I now have a local copy, although the process was far from easy and many pages and links are still missing.
  6. papry

    Galaxian and new Arcade Blaster 1.2 app

    Pleased to find this thread... A few weeks ago, having read another thread in this forum about Atari Centipede, I got the code running on a Papilio Pro with Arcade MageWing. It worked but there were a number of problems which had been pointed out by the person who ported the code, the biggest of which was heavily distorted sound. Since the hardware was by my side, for some reason I was looking in the Papilio One folder on my hard drive and saw a number of arcade downloads, and I decided to have a go at getting Galaxians to work. I setup a new project and made a UCF (all unnecessary as the project file and UCF already existed - doh!) and having found the romgen script, was able to get the code to compile and load. It worked, but the screen was drawn twice. The solution was in this thread, which I implemented and then had good video. I noted that the explosion sound when the ship is hit was missing, and again reading this thread I saw that @alex had not only posted an explaination, but also modified code. So I then tried out his code. It took a little searching to figure out how to create the missing ROM files (which required the updated romgetn script), and I had to remove the PS2 code and replace it with code for the Arcade MegaWing, but this was pretty straightforward. It finally compiled and all appears to be working properly. Many thanks to all involved.
  7. papry


    A bug thumbs up to @james1095 . Just for a quick thing to do on a Saturday afternoon while listening to the football (UK) on the internet, I downloaded the Github original respository. I was pleased to see Verilog source files, but the organisation wasn't great and documentation was sparse. So I downloaded the ZIP file (above), and made changes to the UCF to implement on a Papilio Pro with Arcade megawing. I had the usual problems of having to re-generate the RAMs and DCM, and even now I get some strange warnings about missing files related to the RAM and DCM blocks, however it does compile, download and work over VGA. It would be nice to get audio working and I will take a look at this in the next week or so. I also found out that one of the buttons causes the game to freeze, and the reset button can't recover from this.
  8. Sorry, not really the right place to ask. I haven't visited the forum for some time, and I see that there are quite a few spam postings, which I'm surprised haven't been deleted. So I checked twitter and see that there hasn't been a @gadgetfactory tweet since Feb 2017. So just wondering is Jack OK? I'm a big fan of the Papilio FPGA boards as this was my first FPGA dev board purchase, and I have had much fun and learnt quite a lot since then, despite having lots of problems when I initially tried to get my Papilio One to do something :-). All sorted now! I was kind of hoping that there might be some new Papilio boards using newer FPGAs, but I guess this is now very unlikely :-(. regards... --Papry
  9. Spotted something on Ebay UK and though others might be interested. "Papilio Pro FPGA with Arcade Megawing (Xilinx Spartan 6)" but it now @ £64.99. Seems good value to me. Note: I have absolutely no connection with the seller. Out of interest I searched for "Papilio FPGA" on Amazon UK. "SeeedStudio Papilio Duo-2Mb Fpga On The Top Atmega32U4 On The Botom DIY Maker Open Source BOOOLE" @ £188 ($245). Ouch! "Papilio Duo-2Mb" @ £201 ($262). ...and various other overpriced Papilio related boards.
  10. papry

    Changing the clock frequency

    Just a quick comment that to generate a slower clock, a preferred method is to use a synchronous counter. This type of counter has all counter flops clocked by the same high speed input clock and fits well with the way that FPGAs handle clocks. It is also the way that this type of circuit would be designed in an ASIC. Here is some code I wrote recently (as an example). It divides 315MHz from a PLL to 3.57MHz. A divide by 88 is required. reg [6:0] pll315_counter; reg clk357; // create 3.57MHz NTSC clock by dividing 315MHz by 88 always @ (posedge w_clk315) begin clk357 <= (pll315_counter<7'd44); if (pll315_counter==7'd87) begin pll315_counter <= 7'b0; end else begin pll315_counter <= pll315_counter + 7'b1; end end You would need to change the counter length, termination count and half count to suit your frequencies. I should have really used constants (such as tick defines) rather than hard code numbers, but hey this is my personal hobby project 😃
  11. I have a number of FPGA boards, including several Papilios, and recently acquired a Digilent Artix 7 CMOD A7. The nice thing about this board is the form factor (can plug into a breadboard), and the inclusion of a large SRAM (not SDRAM!). I found a number of projects on Hamsters web pages (excellent learning material BTW), specifically a project to use this board to output 1080p over a HDMI cable. I have spent the past few evenings converting the VHDL code into Verilog. It's not that difficult. I think that I have spotted a bug where the constant 720 is used instead of 1080 (the video is 1080p, but perhaps the code was original for 720p?). I have brought hsync and vsync out to pins in order to check timings on a scope (that's how I found the bug). I was puzzled as to why I was seeing no signals whatsoever on the high-speed TDMS differential pins, until I finally realised that they need 50ohm pull-ups to +3.3V. This is normally done at the other end of the HDMI cable, but I don't have one currently connected. I popped in some resistors and finally saw some waveforms on the differential pins. They were pretty nasty. I really need a scope with much higher bw! Just today I got a HDMI breakout board, ordered from Ebay. I will now be able to connect a HDMI cable to a monitor. To get started I really want to drop down the timings from 1080p to 576p (UK 50Hz standard definition), but I can't find the pixel numbers for the vsync, front/back porch etc. If anyone has a definitive list, please let me know! I can compile for either 1080p or 640x480 VGA timings (no idea if this will be recognised over HDMI). At 1080p I am failing timing analysis. This is where I struggle. I am using a PLL to boost the 12MHz xtal to the 100MHz needed by the original code. I am trying to define in the XDC the clocks. I know how to define the XTAL clock, but I am having problems telling Vivado about the internal clocks. In fact I am not sure whether I really need to or whether it can infer the clocks from the MCM parameters? I tried using the timinng constraints wizard, but it wanted to add constraints for the TMDS outputs, but I had no idea what numbers to use. Any guidance from anyone who has played with HDMI would be greatly appreciated. Once I have something (low res) working with the CMOD-A7 I will go back to the Papilio Pro and get something working here.
  12. papry

    VGA Wing (6 bit)

    OK Dave. I am not a prolific poster, but it did pass my mind to post some pictures once the project had developed. BTW I do have a habit of not finishing things off. If it is Papilio specific I will post here, otherwise I will post to Stardot (where I am user acory). --Gary
  13. papry

    Why 32MHz XTAL?

    Excellent idea! Like all good ideas they are simple and obvious (in hindsight)! I need 65MHz, but I can see several ways to get there with 2 DCM_SPs. Many thanks Alvieboy.
  14. papry

    VGA Wing (6 bit)

    Ah! OK. It is not a problem. I probably can get someone at work to replace the resistors. BTW I am in the UK. The MC6847 chip which I am trying to emulate, only supported limited colours anyway. The project is part of emulating an old UK 6502 "Acorn Atom" computer. Someone has already done an excellent full port of this computer to the Papilio (known as Hoglet on the BBC/Acorn forum, and on this forum too). For me it is simply a for fun and learning project. I will connect the Papilio One to a real (3.3V) 65C02, and 64k bytes RAM, rather than emulate them in the FPGA. The only problem is that I will probably run out of FPGA pins (16 needed for the address and 8 for the databus, leaving only 8 for other 65C02 and RAM pins). The idea was to connect to a real (old) X,Y matrix keyboard which I have, but this could be a problem :-). I guess I might have to wait for the Papilio Pro Plus to be released which hopefully will have far more pins!
  15. papry

    VGA Wing (6 bit)

    Sorry if I wasn't clear. All 3 VGA colour analogue inputs connect to 2 FPGA pins via resistors of the exact same value (marked 271 - using a magnifying glass). I was expecting one resistor to be half the value of the other. So code 00 is black, code 11 is full intensity (luminance), but codes 10 and 01 result in the same luminance. On the bottom is appears to be make by Sparkfun. On the MegaWing there are 3 resistors for the red and green channels (2k, 1k and 510 ohms). They form a potential divider with the 75 input impedance of the monitor. On the Altera board there are 5 resistors per channel (similarly 500, 1k, 2k, 4k and 8k ohms). I made a project which simply ramped the count from 0 to 31 and viewed the voltage on a scope. I was surprised to see that code 15 (01111 binary) was at a higher voltage than code 16 (10000 binary). In this simple scheme I suspect that the output impedance of the FPGA driver has not been taken into account, and has an impact. I tried different drive strengths and the ramp steps did change in the area of the 15 to 16 transition.