# Myndale

Members

5

## Posts posted by Myndale

1. ### VHDL processes

Thanks Thomas, appreciate the feedback.

In hindsight I shouldn't have used a combinatorial circuit as my example, because my question was meant to be specifically about processes. From your feedback, and what I've seen elsewhere, it sounds like I'm over-thinking things and worrying about issues that aren't as important as I thought they were. And that's fine, because that's also a perfectly valid answer to my question, so thanks again!

2. ### VHDL processes

Hi everyone,

I have a beginner question about VHDL processes. Let's say, for the sake of argument, I want to synthesize something like a TTL 7400 chip (i.e. quad nand gate). An initial attempt might involve doing something like this:

```	process(A1, A2, A3, A4, B1, B2, B3, B4)
begin
Y1 <= A1 nand B1;
Y2 <= A2 nand B2;
Y3 <= A3 nand B3;
Y4 <= A4 nand B4;
end process;
```

It would seem to me that the long dependency list wouldn't make this terribly efficient, at least not during simulation, and that ideally processes should maybe try to do something like this:

```	process(A1, B1)
begin
Y1 <= A1 nand B1;
end process;

process(A2, B2)
begin
Y2 <= A2 nand B2;
end process;

// ...etc...
```

So my first question is "am I correct in my understanding of this?", i.e. is it indeed a good idea in general to separate logic into different processes like this? Or is there some overhead associated with processes that makes it inadvisable for simple cases? And if so, where's the cross-over point?

Or should I forget about focusing so much on simulation and instead concentrate on trying to help synthesis? E.g. something like this...

```	-- A, B and Y are now all std_logic_vector(3 downto 0)
process(A, B)
begin
Y <= A nand B;
end process;```

...which technically is the same as my first example above (I think) but would usually wind up in a more efficient circuit (I think)?

I hope these questions aren't too vague, just trying to get my head around best practices. Thanks in advance for any advice and general guidance.

3. ### DCMs and static timing

Thanks Jack, that works fine. Not sure how I missed those multiple output options in the wizard...a case of not seeing the forest for the trees I guess!

4. ### DCMs and static timing

Thanks for the feedback, it looks like I was indeed not understanding the timing report correctly. Time to go hit the docs again.

And thanks for the helpful tip Jack. I've created a double-buffer in BRAM so I can draw one scan line while the previous one is being drawn by my VGA signal generator. My draw circuit is running at 100MHz and I'm using a 2-bit logic vector to down-sample this to 25MHz for my signal generator. Am I correct in the understanding that I can simply put my signal generator in it's own module and give it a 25MHz timing constraint? The fact that I'm generating the 25MHz clock from the 100MHz clock (as opposed to creating a second DCM clock) won't somehow cause problems, will it?

5. ### DCMs and static timing

I'm just starting out with FPGA's so apologies if this is a bit of a noob question but I'm having trouble understanding the relationship between DCM clocks and their effect on static timing.

I've designed a circuit to run at 100MHz. If I run it directly off the 32MHz Papilio Pro clock the static timing report states a minimum period of 4.992ns/200.321MHz. However, as soon as I add a DCM to bump the clock up to 100MHz the report drops to 16ns/62.5MHz, even though the circuit itself appears to operate fine at that speed. Furthermore this DCM timing result remains the same even If I strip my design down to a single flip-flop.

I'm assuming that either I'm setting something wrong in the DCM core generator or I'm misunderstanding the static timing report (i.e. it applies to the incoming clock, not the DCM output). If the former, can anyone suggest what I might be doing wrong? If the latter, how do I go about testing the maximum frequency of my designs without disconnecting them from the DCM every time?