• Content count

  • Joined

  • Last visited

Community Reputation

0 Neutral

About ralph

  • Rank

Profile Information

  • Gender
  1. It's some cheap non-branded monitor that doesn't like what it considers to be non-standard refresh rates. Anyway, it all works at 640 x 384 x 60. Just one question - if 1024 x 768 x 60 is not possible with a DUO, is there any chance that 1024 x 768 x 30 could work? A higher resolution with a lower refresh rate would be handy.
  2. OK, forgot to upload the circuit before trying to load the AVR program. All is well now (well, 90% - my monitor is displaying not supported, but otherwise, basically drawing most of the input with some off-screen). Anyway, it's basically working thanks.
  3. Thanks, Jack. I was selecting Papilio Duo - AVR instead of Papilio Duo FPGA 2MB. I've also selected the COM port. Now that I have fixed that, however I get a different problem Cannot get programmer version, aborting Could not contact ZPUino embedded programmer.The more common reasons for this are: a) You are not specifying the correct port. The port currently selected is 'COM15' The board FPGA is not programmed with a valid ZPUino bitfile.c) The board is properly not powered. Please review all of above, if problem persists please contact support.
  4. OK, even fixed the ZPUino_GFX.h erro, but now it can't find pll.h. There are too many possibilities for fixing that, so I guess I need to wait until Alvieboy / Jack fix up DesignLab to include the necessary libraries...
  5. OK, I fixed that by downloading the Adafruit =GFX library and putting it in the libraries folder, but now I am getting Demo.ino:33:24: fatal error: ZPUino_GFX.h: No such file or directorycompilation terminated. Seems like some needed files are not included with DesignLab 1.0.4. Hopefully they can be included in the next release...
  6. I've got a Papilio Duo with a Logic Start shield. In DesignLab 1.0.4, I selected ZPUino_VGA_Adapter, and then edited the source so that it corresponded to Duo + Logic Start Shield, commenting out the other options. However, it now says Build options changed, rebuilding allDemo.ino:32:26: fatal error: Adafruit_GFX.h: No such file or directory I guess this is a simple fix: how do I proceed? Thanks! Ralpg
  7. ralph

    USB Issue on AVR side.

    Just to rule one thing out for you: I am successfully using a DUO on a Mac with Windows under Parallels. I did have some strange issue at first where I too could not get files to stick, but it cleared itself, and I cannot readily remember what I did.
  8. ralph

    LogicStart Shield for the Papilio DUO

    Agreed. Having got over the hurdle of how to get started, I'm having great fun. So far I've been playing some square waves through the audio port, doing a counter on the 7 segment leds, and other little things to get up to speed on FPGAs - I've been trying drawing circuits, and writing them in VHDL and Verilog. At the moment, I'm mainly sticking to using the FPGA side without the ZPUino (Hey, I know the point is that I can combine code for the ZPUino or AVR and draw circuits with ISE, but I already know about arduinos and programming, so wanted to do some new stuff!) Nice board, and nice software.
  9. Great! That's probably easier to follow.
  10. Great, thanks. The project works fine, but I was a little puzzled at first to find only 5 OBUFs when I expected 8! Then I realised what is going on. Arduino outputs 0,1,2,3,4 connect to FPGA inputs then go via OBUFs to FPGA outputs labelled Arduino 48,50,52,5,6, to drive LEDS 0-4. However, the Arduino drives pins 7,8,9 directly as LEDs 5-7 are connected to those pins. The FPGA is not involved for these signals. So, some lines go via the FPGA, and others don't. Tricky! Anyway, thanks Jack, this is all becoming a lot clearer now. I'm sure these examples will help plenty of others too.
  11. Thanks Jack, that's much appreciated. If you look at my "Almost working" post in this forum, you'll see I managed after a bit of head scratching to get a counter running on the AVR displaying on the Logic Start Shield after piping the data through the FPGA (as a test). Now I'll compare my idea to yours...
  12. OK, I think I have got it. Some pins listed for "Arduino" are only for the Arduino Core running on the FPGA, not for the AVR, which has fewer outputs than the Arduino Core. So, it looks like my plans to drive the FPGA from the AVR will be have to be revised. I guess I can repurpose some of the Logic Start Shield directional buttons which seem to be connected to the AVR. Postscript: I did exactly that and it all now works fine. Data is now transferred on AVR/Arduino pins {0,1,2,3,4,10,11,12} NET SW(5)-SW(7) now connect to pins P131, P132, P133. Phew.
  13. Hi. I am trying to make a simple project in which the (real) AVR sends data to the FPGA, which in turn outputs it on the LogicStart Shield LEDs (as a proof of concept before trying something more complicated): The arduino AVR program increments a counter every 100ms, whose value is output to the Switch positions on the logic shield. The arduino output pins used for counter bits 0 to 7 in turn are {0,1,2,3,4,42,44,46}. (Shield switches are all up as per instructions; other Arduino pins are set as inputs to prevent any clashes). An FPGA schematic then connects the Switches to the LEDs on the Logic shield, to display the counter. It's almost working but not quite. The low order 5 leds show the count as it increments, as intended, but the 3 high order leds are always on and do not change. The part of the UCF which maps these inputs to the LEDs via LED <= SW looks like NET SW(0) LOC="P116" | IOSTANDARD=LVTTL;NET SW(1) LOC="P117" | IOSTANDARD=LVTTL;NET SW(2) LOC="P118" | IOSTANDARD=LVTTL;NET SW(3) LOC="P119" | IOSTANDARD=LVTTL;NET SW(4) LOC="P120" | IOSTANDARD=LVTTL;NET SW(5) LOC="P62" | IOSTANDARD=LVTTL;NET SW(6) LOC="P59" | IOSTANDARD=LVTTL;NET SW(7) LOC="P57" | IOSTANDARD=LVTTL;NET LED(0) LOC="P55" | IOSTANDARD=LVTTL;NET LED(1) LOC="P50" | IOSTANDARD=LVTTL;NET LED(2) LOC="P47" | IOSTANDARD=LVTTL;NET LED(3) LOC="P121" | IOSTANDARD=LVTTL;NET LED(4) LOC="P123" | IOSTANDARD=LVTTL;NET LED(5) LOC="P124" | IOSTANDARD=LVTTL;NET LED(6) LOC="P126" | IOSTANDARD=LVTTL;NET LED(7) LOC="P127" | IOSTANDARD=LVTTL; Apart from renaming the nets and omitting some stuff about drive and slew, these look to be the same as in the Logic Shield ucf. However, I have also left other definitions in from the standard papilio duo ucf, as if I omit them, the AVR's programming port no longer shows up. I'm wondering if there is some clash of use of pins here? However, the logic start shield does say you are free to connect a wing to the switch pins, which makes me think my approach should work. Any insight as to what is going wrong gratefully received - and I suspect it will help other beginners to who are trying to pass data from the AVR into the FPGA. Ralph
  14. ralph

    LogicStart Shield for the Papilio DUO

    Thanks, Jaxartes - I think something like that could well be the answer. I seem to remember when it wasn't working, the pin assignments didn't look as expected even though the UCF file was present. Perhaps there's some trick to making the UCF file "stick".