Haider

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Posts posted by Haider


  1. I make the change

     

    and this is my UCF file

    ## Clock signalNET "clk"            LOC = "V10" | IOSTANDARD = "LVCMOS33";   #Bank = 2, pin name = IO_L30N_GCLK0_USERCCLK,            Sch name = GCLKNet "clk" TNM_NET = sys_clk_pin;TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 25000 kHz;## VGA ConnectorNET O_VIDEO_R<0>         LOC = "U7"  | IOSTANDARD = "LVCMOS33";  NET O_VIDEO_R<1>         LOC = "V7"  | IOSTANDARD = "LVCMOS33";   NET O_VIDEO_R<2>         LOC = "N7"  | IOSTANDARD = "LVCMOS33";   NET O_VIDEO_G<0>         LOC = "P8"  | IOSTANDARD = "LVCMOS33";NET O_VIDEO_G<1>         LOC = "T6"  | IOSTANDARD = "LVCMOS33";NET O_VIDEO_G<2>         LOC = "V6"  | IOSTANDARD = "LVCMOS33";NET O_VIDEO_B<0>         LOC = "R7"  | IOSTANDARD = "LVCMOS33";NET O_VIDEO_B<1>         LOC = "T7"  | IOSTANDARD = "LVCMOS33";NET "Hsync"          LOC = "N6"  | IOSTANDARD = "LVCMOS33";                           NET "Vsync"          LOC = "P7"  | IOSTANDARD = "LVCMOS33";                          #NET "vgaRed<0>"      LOC = "U7"  | IOSTANDARD = "LVCMOS33";   # Bank = 2, Pin name = IO_L43P,                          Sch name = RED0#NET "vgaRed<1>"      LOC = "V7"  | IOSTANDARD = "LVCMOS33";   # Bank = 2, Pin name = IO_L43N,                          Sch name = RED1#NET "vgaRed<2>"      LOC = "N7"  | IOSTANDARD = "LVCMOS33";   # Bank = 2, Pin name = IO_L44P,                          Sch name = RED2#NET "vgaGreen<0>"    LOC = "P8"  | IOSTANDARD = "LVCMOS33";   # Bank = 2, Pin name = IO_L44N,                          Sch name = GRN0#NET "vgaGreen<1>"    LOC = "T6"  | IOSTANDARD = "LVCMOS33";   # Bank = 2, Pin name = IO_L45P,                          Sch name = GRN1#NET "vgaGreen<2>"    LOC = "V6"  | IOSTANDARD = "LVCMOS33";   # Bank = 2, Pin name = IO_L45N,                          Sch name = GRN2#NET "vgaBlue<1>"     LOC = "R7"  | IOSTANDARD = "LVCMOS33";   # Bank = 2, Pin name = IO_L46P,                          Sch name = BLU1#NET "vgaBlue<2>"     LOC = "T7"  | IOSTANDARD = "LVCMOS33";   # Bank = 2, Pin name = IO_L46N,                          Sch name = BLU2

    I try both this like

    TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 25000 kHz;

    and nothing change, I got black screen everytime

     

    so is there problem in adjusting the Clock Frequency or there is another way to write it?

     

    2uiVESh.jpg?1

     

     

    GfM79Un.jpg?1

     

    WN7Ercn.jpg?1

     

    Y2UNGGl.jpg?1

     

    Ly4pR2h.jpg?1


  2. I think the same thing will happen with Papilio Pro if I want to Implement this code on it, Pro has also 3 Pins for Red, Green and 2 for Blue.

    NET VGA_BLUE(0)    LOC="P92"  | IOSTANDARD=LVTTL;                                # B2NET VGA_BLUE(1)    LOC="P87"  | IOSTANDARD=LVTTL;                                # B3NET VGA_GREEN(0)   LOC="P84"  | IOSTANDARD=LVTTL;                                # B4NET VGA_GREEN(1)   LOC="P82"  | IOSTANDARD=LVTTL;                                # B5NET VGA_GREEN(2)   LOC="P80"  | IOSTANDARD=LVTTL;                                # B6NET VGA_RED(0)     LOC="P78"  | IOSTANDARD=LVTTL;                                # B7NET VGA_RED(1)     LOC="P74"  | IOSTANDARD=LVTTL;                                # B8NET VGA_RED(2)     LOC="P95"  | IOSTANDARD=LVTTL;                                # B9

    Rhe source code for Nexys 3 board in the attachment,

    vga7seg.zip


  3. The original source code got it from this link but there is some problem to download it so I suggest to download it from the attachment, I didn't make any change,
     
    http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/logicstart-megawing/virtual-7-segment-display-on-vga-r37
     
    Also I upload the UCF file for Nexys 3 board to make the code work on Nexys3

    nexys3_master_ucf.zip

    vga7seg-master.zip


  4. with this change

    begin	-- connect internal video signals to outputs	VideoR <= O_VIDEO_R(0) & O_VIDEO_R(1) & O_VIDEO_R(2);	VideoG <= O_VIDEO_G(0) & O_VIDEO_G(1) & O_VIDEO_G(2);	VideoB <= O_VIDEO_B(0) & O_VIDEO_B(1);

    I get this :D

    ERROR:HDLCompiler:288 - "C:\vga7seg\source\seven_segment_top.vhd" Line 46: Cannot read from 'out' object o_video_r ; use 'buffer' or 'inout'ERROR:HDLCompiler:288 - "C:\vga7seg\source\seven_segment_top.vhd" Line 47: Cannot read from 'out' object o_video_g ; use 'buffer' or 'inout'ERROR:HDLCompiler:288 - "C:\vga7seg\source\seven_segment_top.vhd" Line 48: Cannot read from 'out' object o_video_b ; use 'buffer' or 'inout'ERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 97: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 98: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 99: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 100: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 101: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 102: Indexed name is not a std_logic_vectorERROR:HDLCompiler:854 - "C:\vga7seg\source\seven_segment_top.vhd" Line 23: Unit <rtl> ignored due to previous errors.

    and this change

    begin	-- connect internal video signals to outputs	  O_VIDEO_R <= VideoR(0) & VideoR(1) & VideoR(2);	  O_VIDEO_G <= VideoG(0) & VideoG(1) & VideoG(2);	  O_VIDEO_B <= VideoB(0) & VideoB(1);

    give me different errors (less errors :blink: )

    ERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 97: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 98: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 99: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 100: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 101: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 102: Indexed name is not a std_logic_vectorERROR:HDLCompiler:854 - "C:\vga7seg\source\seven_segment_top.vhd" Line 23: Unit <rtl> ignored due to previous errors.

  5. Hi,

     

     

    I read the title of this thread and enter to see ... I'd like to take a place in this discussion if you don't mind please,

     

    I have the same question about FPGA, before I start learning FPGA I was playing with MCU like AVR, Parallax Propeller 8 core

    I understand C/C++ and can implement any idea in embedded system device,

     

    I move to FPGA because I read in some of university program for MSc there is FPGA lectures in Embedded system course beside MCU lectures, I want to know the reason so that's why start learning FPGA and buy my first FPGA, but to be honest with you i don't want to learn something for fun only I want to love it and be an expert in that field to get professional job in the future, All what I see in this form is re implement some of exist hardware chip on FPGA like ZPUino or other circuit, there is no new invention forget that let’s talk about professional member in this forum like Alvie or Hamster the programming FPGA at least before 10 year ago and everyone is expert in FPGA what is the best thing that they did, Alvie if I'm not wrong make the ZPUINO and its Re-implement of ZPU soft core, Hamster make the FPGA board and provide FPGA lecture in his website,if we want to convert the ZPUINO into ASIC chip it will never be a competitor against Atmel328p I can’t imagine the Energy consumption and number of Transistors in ZPUNIO is much more and it's need a lots of optimizing, if these people with their experience can't make chip like Atmel328p so why the spend their time to continue using FPGA, also how about person like me who start from scratch trying to be successful FPGA engineer,

     

    I Understand FPGA not using only in ASIC Design, can someone tell me anyone in this forum have a job deals with FPGA, if there is no problem can I ask about Hamster job or Alvie are they FPGA engineer in real life or their job is difference and they learn FPGA and become professional for fun only,

     

    I want to ask this question and many other question before long time because I'm so Confuse between choosing the right direction for my future work and field,

     

    I Believe if someone want to be successful in something then he should become a specific in that field not Embedded System programmer in C/C++ and FPGA engineer VHDL and Verilog in the same time, I believe the professional engineer in NXP, Nvidia, Samsung, everyone has his specific job and don't deal with other who have difference job, if anyone have another idea or I say something wrong I will be so interesting to know his opinion about what I say.


  6. I deactivate this lines
     

    begin    -- connect internal video signals to outputs    O_VIDEO_R <= VideoR;    O_VIDEO_G <= VideoG;    O_VIDEO_B <= VideoB;

    and make this changes

    begin    -- connect internal video signals to outputs    --O_VIDEO_R <= VideoR;    --O_VIDEO_G <= VideoG;    --O_VIDEO_B <= VideoB;    VideoR <= O_VIDEO_R[0] & O_VIDEO_R[1] & O_VIDEO_R[2];    VideoG <= O_VIDEO_G[0] & O_VIDEO_G[1] & O_VIDEO_G[2];    VideoB <= O_VIDEO_B[0] & O_VIDEO_B[1];

    but still get this error

    ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 46: Syntax error near "0".ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 47: Syntax error near "0".ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 48: Syntax error near "0".ERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 98: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 99: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 100: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 101: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 102: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 103: Indexed name is not a std_logic_vectorERROR:HDLCompiler:854 - "C:\vga7seg\source\seven_segment_top.vhd" Line 23: Unit <rtl> ignored due to previous errors

    also I try to rewrite the line in difference way
     

    begin      -- connect internal video signals to outputs      --O_VIDEO_R <= VideoR;      --O_VIDEO_G <= VideoG;      --O_VIDEO_B <= VideoB;      O_VIDEO_R <= VideoR[0] & VideoR[1] & VideoR[2];      O_VIDEO_G <= VideoG[0] & VideoG[1] & VideoG[2];      O_VIDEO_B <= VideoB[0] & VideoB[1];

    and still get this error
     

    ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 50: Syntax error near "0".ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 51: Syntax error near "0".ERROR:HDLCompiler:806 - "C:\vga7seg\source\seven_segment_top.vhd" Line 52: Syntax error near "0".ERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 97: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 98: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 99: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 100: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 101: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 102: Indexed name is not a std_logic_vectorERROR:HDLCompiler:854 - "C:\vga7seg\source\seven_segment_top.vhd" Line 23: Unit <rtl> ignored due to previous errors.



     


  7. Thanks for explain , Now I see this much complicated than what I expect,

     

    I have  Intro to Spartan FPGA eBook about FPGA, I print it on A4 paper  :lol:  and read 3 or 4 paper in home or work when I have time but till now I didn't done 15% of the book so I thing I'm still newbile to understand your answer, it's really different when someone move from MCU to FPGA but I'll continue try.

     

    Thanks for helping Jaxartes.


  8. thank, I believe your answer solve my problem but I'm newbie in FPGA and I use it for do very simple example in my home like connect button and try to implement some gate when the board receive signal the led turn on and something like this,

     

    my problem is :D I don't know how to "make small changes to the syntax of the VHDL code" and don't understand what is that mean "you should probably connect the single bit to the msb of the multibit and set the non-msbs to zero.",

     

    Al last thanks for helping I was thought it will be easy to write hello world by using FPGA connected to LCD via VGA.


  9. Hi,

    I'm trying to implement  Virtual 7 Segment display on VGA VHDL code on Nexys 3 board

    this code implemented on Papilio One with Megawing Shield

    http://forum.gadgetfactory.net/index.php?/page/articles.html/_/papilio/logicstart-megawing/virtual-7-segment-display-on-vga-r37


    I change the VGA pinout in UCF file but there is something I don't understand it that Nexys 3 have 8 pins for VGA adapter

    3 for green
    3 for red
    2 for blue
     

    NET "rgb[7]" LOC = U7 | IOSTANDARD = LVCMOS33;NET "rgb[6]" LOC = V7 | IOSTANDARD = LVCMOS33;NET "rgb[5]" LOC = N7 | IOSTANDARD = LVCMOS33;NET "rgb[4]" LOC = P8 | IOSTANDARD = LVCMOS33;NET "rgb[3]" LOC = T6 | IOSTANDARD = LVCMOS33;NET "rgb[2]" LOC = V6 | IOSTANDARD = LVCMOS33;NET "rgb[1]" LOC = R7 | IOSTANDARD = LVCMOS33;NET "rgb[0]" LOC = T7 | IOSTANDARD = LVCMOS33;

    While in the "Virtual 7 Segment display on VGA VHDL code" the author use only 1 pin for each color, Also mega wing schematic have the same thing there are primary pins VGA adapter and secondary pins (3 pins for green and red while blue got 2 pins)

    I make some change in the code to make it work in Nexys 3 FPGA board like changing the Entity from

    STD_LOGIC to STD_LOGIC_VECTOR (2 downto 0)

    But I still get this error

    ERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 88: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 89: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 90: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 91: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\vga7seg\source\seven_segment_top.vhd" Line 92: Indexed name is not a std_logic_vectorERROR:HDLCompiler:539 - "C:\Uvga7seg\source\seven_segment_top.vhd" Line 93: Indexed name is not a std_logic_vectorERROR:HDLCompiler:854 - "C:\vga7seg\source\seven_segment_top.vhd" Line 23: Unit <rtl> ignored due to previous errors.


     

    vga7seg.zip


  10. Hi,

     

    last day I was interesting to implement VGA driver in FPGA using Papilio board there is a tutorial written by alvie about using ZPUINO to drive VGA LCD display, it's a great tutorial for newbie and beginner but it's like using Arduino with some line of c code to show hello world,

    I want something written in VHDL, by the way I find this one

     

    http://papilio.cc/index.php?n=Playground.VGAGenerator

     

     

    VGA_Text_Generator1.jpg

     

    written by Kevin Lindsey   after download the source code for Github, I try to implement the top module for VGA Text when I use Xilinx 14.5 when I open the vga_text.xise I got this message image.png

     

    I choose Backup and Migrate   When I try to implement the top module I got this error

    image.jpg

     

    Why this error show to me also I want to ask some question about this source code because I want to understand the fundamentals of how it’s work Q1/ I  understand this file like font library for the character used to show on display  font_unit - font_rom - arch (font_rom.vhd) as example     

    		-- code x32		"00000000", -- 0		"00000000", -- 1		"01111100", -- 2  *****		"11000110", -- 3 **   **		"00000110", -- 4      **		"00001100", -- 5     **		"00011000", -- 6    **		"00110000", -- 7   **		"01100000", -- 8  **		"11000000", -- 9 **		"11000110", -- a **   **		"11111110", -- b *******		"00000000", -- c		"00000000", -- d		"00000000", -- e		"00000000", -- f

      This code used to print 2 on screen but how to call it I mean the way to print number 2 by call “code x32” or what ? Can someone explain to me how to print hello world by using this code on screen and how to change its location or color


  11. hi again

     

    this time i have general guestions about fpga but before i start asking i want to post what i found in my search about FPGA with USB

     

     

    USB-FPGA Module 2.16: Artix 7 XC7A200T FPGA Board with USB 2.0

    http://www.ztex.de/usb-fpga-2/usb-fpga-2.16.e.html

     

    this borad come with the higest chip in artix 7 family

    also with usb2 port and they say in spec tech:

    • High-Speed (480 MBit/s) USB interface via Mini-USB connector (B-type)

    price little high about 550 $ or 525 $

     

     

    but this board does not contain anytime of RAM i read the spec tech and download the resources info for this board but didn't find any thing refer to ram(SRAM, DRAM ,DDR, etc...)

     

    Q/ how this will going to work ?

     

    Q2/till now the perfect board have USB 3  with powerfull FPGA spartan LX150T is opil kelly xem6310 but it's expensive

    cost about 800 $

     

    i now this question is too far for someone newbie like me, but i want to learn more about hardware and FPGA

     

    digikey and other website is like wikipedia for electircal and electronic engineer

    i visit it to read and disconver what is the type of chip and how many cassification can we make for the digital and analog chip

     

    by the way  lets try to pick some chip form digikey

     

    USB3 Controller : Cypress Semiconductor Corp CYUSB3014-BZXI

    Cost : $37.44

     

     

     

    FPGA Chip :  Xilinx Artix-7 XC7A200T-1FBG484I (this more powerfull than Spartan 6 LX150T)

    Cost: $213.75

     

     

    RAM : Alliance Memory, Inc. AS4C512M8D3L-12BIN (while XEM6310-LX150 have DDR2 128 MiB)

    and this LDDR3 RAM 800 Mhz

    Cost: $12.15

     

    by the way in the spect tech table in digikey what is that mean

     

    Memory Size4G (512M x 8)

     

    sometimes 256x16

    is that mean they will sell you 8 or 16 chip and every chip is 512 or 256 or what

     

     

     

     

    Total Cost for this three chip is : $251.19

     

    all this chip is more power than XEM6310-LX150 expect usb3 controller

     

    i now we still need resistor and other component like ROM so we can say the other component will not cost more than 100 $

    lets say it will be 100$

     

    the total cost for all items will be

     

    362 $

     

    with this budget can we design FPGA board more powerfull and less cost than XEM6310-LX150

     

    how much the print PCB and asselmbly part (with SMD chip) will cost

     

    will 500 be enough to order one board only

    i dont ask this question because i want to do that but just i want to have an idea about PCB Design and production cost

    thats all

    i know order 1 board will cost to high than many board

     

     

     

     

     

     


  12. Hi Dove

     

    i send magnus email about this:-

     

    "BTW, if you are interested in Pipistrello then I can offer you a used v1 board with an LX9 chip and 166 MHz LPDDR memory for $45. It can do up to 28 MB/s transfer rate between the computer and the FPGA, and I have code for both the computer and the FPGA that can be used as a starting point for your project. Email me (magnus at saanlima dot com) if you need more info."

     

     

    and if there is any question or something have information about FPGA, MCU, Chip I'll post it in this thread.

     

     

    my regards


  13. mkarlsson im really grateful from you for this info, thank you very much

     

    Pipistrello Rev 2.0 i great board this Hardware Description from its website :-

     

    FPGA: Spartan-6 LX45 in 324 BGA package, speed grade -3C

    Flash memory: 128 Mbit SPI flash memory (Micron N25Q128A13ESE40G) wired for 1x, 2x or 4x wide data path

    On-board DRAM: 64 MBytes (32Mx16) of LPDDR memory (Micron MT46H32M16LFBF-5) clocked at 200 MHz (up to 800 MBytes/s transfer rate) in 60 BGA package

    USB device interface: High-speed (480 Mbits/s) interface using a 2-channel FTDI FT2232H chip. Channel A is wired for JTAG. Channel B is wired for serial or async FIFO mode.

    DVI/HDMI interface: Full HDMI output interface (including I2C level translators for DDC) using a 19-pin HDMI type A connector

    Audio output: Two-channel audio output using 1-bit sigma-delta DAC

    Micro-SD card: Socket for micro-SD card, wired for SPI or native (4x wide) SD interface

    PMOD interface: Double-row PMOD connector that will allow the use of a wide range of PMOD devices (see below for more info on PMOD devices)

    LED indicators: Power (green), config state (yellow), five user-defined

    User I/O: Papilio-style wing interface with 48 user-defined I/O signals. The boards have female headers installed on the wing interface.

    Form factor: Similar to Papilio One (2.9" x 2.7")

    Fully supported by Xilinx tools (iMPACT, Chipscope, SDK etc.) without need for Xilinx JTAG cable.

    Assembled and tested in USA

     

    ------------------------------------------------

     

     

    as you say it can reach the 480 mbp/s for USB 2.0 opalkelly offer many options with great spec tech there is spartan 150, vertix 5,7 and Kintex-7, Altera Cyclone IV (but some of them out of my budget till in the future :D )

     

    my next step is search and know more about opalkelly boards and Pipistrello, but because you are here, im geek in ask you and i'm filled happiness  :wub:  because of your answer

     

    what do you thing about this board

     

    fist one

     

    Basys™3 Artix-7 FPGA Board

    http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1288&Prod=BASYS3

     

     

    this three share the same thing

     

    ZYBO Zynq™-7000 Development Board
     
     
    ZedBoard  Zynq™-7000 Development Board
     
     
    Nexys™4 DDR Artix-7 FPGA Board
     
     
    the first two have:
    • OTG USB 2.0 PHY (supports host and device)

     

     

    so my question will this board offer high speed USB data transfer  like the two you suggested to me.

     

     

     

     

     

     


  14. i search in the internet and find this thing

     

    Basys™2 Spartan-3E FPGA Board have "USB 2 full-speed port for FPGA configuration and data transfers (using Adept 2.0 software available as a free download)"
     
     
     
     
    also find this Board
    aes220 high speed USB FPGA mini-module
     
    its spartan 3 and could use the full speed of USB 2.0 port
    what about Duo or Pro with spartan 6
     
    if its depend on the USB Controller Chip
     
    is it possible to use the same chip in these Board above with Duo or Pro
     
     
     
    this article about how to implement high speed USB 2 on FPGA

  15. i want to implement this idea on FPGA i'm trying to send data from PC to FPGA (high bandwidth 20 or 30 MB/s)

     

    to process it inside FPGA by specialized Algorithm to minimize the processing time then send it back from FPGA to PC Via FPGA Board to do that there is FPGA Board with PCI Express slot to receive data with high bandwidth

     

    but its come with Vertix 6 or 5 or 7 FPGA Chip and its price between 1500 and 5000 us $

    so that why i decide to go with USB port to use it instead of PCI Express slot

     

    take an example there is some example in the internet about implement file compression algorithm on FPGA to compress the file in faster time but it use to compress stored data inside FPGA limit size of data not used in real-time mode receive data and process it in the same time

     

    i know this thing classified in the advanced level in FPGA but i want to ask about it because this is what i love and want to learn.

     

     

    my regards


  16. Hi everyone

    i have question about Papilio Duo?
    before i ask the question

    i read FPGA tutorial written by Hamster about sending data between two FPGA board (i think the model was Papilio One 250k) with speed up to 400 Mbps

    i want to trying do the same thing but between FPGA board and my pc

    so my question does the USB port in Papilio Duo support Host Device and Data transfer (maybe that call these things OTG 2.0 PHY)

    like this FPGA boards

    ZYBO Zynq™-7000 Development Board


    https://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1198&Prod=ZYBO

    if you visit the URL you will read in the description they say that the board have

    High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO

    also support

    OTG USB 2.0 PHY (supports host and device)