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About papipro

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  1. Testing progress: Did some testing with an oscillator built from a 74xx04 NOT-gate, the Hamster high speed frequency counter can count to 80MHz, the max speed of the ring oscillator, without problem. I was hoping the ring oscillator can go faster. I am goingto use the FPGA next to see if I can generate a higher frequency. Thanks for your help.
  2. Thank you. I did add the timing constraint " NET "prescaled" PERIOD=2.102;" to fast_freq_counter.ucf. If I understand your reply correctly, prescaled should be the most stringent timing requirement in fast_freq_counter.ucf. So I modified fast_freq_counter.ucf by deleting the timing constraint on test_signal_p. My new fast_freq_counter.ucf is NET clk32 LOC="P94" | IOSTANDARD=LVTTL | PERIOD=31.25ns; # CLK NET TX LOC="P105" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=SLOW; # TXNET test_signal_p LOC = "P51" | IOSTANDARD = LVDS_33;NET test_signal_n LOC = "P50" | IOSTANDARD = LVDS_33;NET "prescaled" PERIOD=2.102; This new constraint file was successfully implemented without generating any warning or error. In Timing Constraints under Design Overview, it said the constraint "NET "prescale" PERIOD=2.102ns High 50%" was met. I am going to see if I can get a function generator to test the counter. Previously, I tested 500MHz version up to 112MHz with IOSTANDARD= both LVDS_33 and LVTTL. I'll let you know in a day or two of the result. Thanks again.
  3. While trying to test Hamster's high speed frequency counter at 950MHz, a "WARNING:Par:468 - Your design did not meet timing" is generated. Per instruction on, I added NET test_signal_p LOC = "P51" | IOSTANDARD = LVDS_33 | PERIOD=1.051ns; NET test_signal_n LOC = "P50" | IOSTANDARD = LVDS_33; NET "prescaled" PERIOD=2.102; to fast_freq_counter.ucf, and modified fast_freq_counter.vhd as followed entity fast_freq_counter is Port ( clk32 : in STD_LOGIC; test_signal_p : in STD_LOGIC; test_signal_n : in STD_LOGIC; prescaled : buffer STD_LOGIC; tx : out STD_LOGIC);end fast_freq_counter; ... process(test_signal) begin if rising_edge(test_signal) then prescaled <= not prescaled; end if; end process; ... i_input_counter: input_counter PORT MAP( test_signal => prescaled, gray_count => gray_count ); According to Design Summary, best case achievable for constraint "NET "test_signal" PERIOD = 1.051 ns HIGH 50%;" is 1.710ns. All other constraints are met. (Unmodified, the original 500MHz vhdl has best case achievable timing of 1.636ns. So the modifications I made make implementation slower.) I seek guidance on solving Par:468 timing error. Thank you for your time.