dandreat

That appears to be the information I was looking for. Thank you very much!

Ah. I think I've found most of what I'm looking for. * The HDL sources are in the hierarchy of the GadgetFactory GitHub Papilio-Schematic-Library/examples/ repository. * And, I've discovered the Windows executable for the server in the GadgetFactory GitHub Papilio-Schematic-Library/examples/Virtual_Dashboard/papilio-prog-jtag-server/ repository. BUT, I can't seem to find the source for the papilio-prog-jtag-server. I think I could understand how this works end-to-end if I could take a look at that. Any tips for where I might find that source would be appreciated. Thanks in advance! dandreat

I posted the query below in the "Open Bench Logic Sniffer with 64MB capture buffer" thread, but perhaps this is a better choice. In the post below, the "server" being referred to is the socket to JTAG over USB/FTDI 'server'; or what Jack is referring to above as "The way this works is that I modified the papilio-prog application to add a jtag passthrough mode, it creates a network socket and will pass communications through to the FPGA:". Perhaps a peek at that code would answer my points 1 and 2 below. I didn't see this passthrough mode in the GitHub files for papilio-prog, but I could have just missed it. From what I gather, it appears that all this may be part of the ZPUino files / library, so I may spend some more time looking there. However, I'm mostly looking for the bare bones HDL and 'C' rather than utilizing schematic entry so as to more easily integrate with my current project. Jack Gassett, on 06 Feb 2014 - 6:02 PM, said: Hi, Jack; I wonder if you might share 1) source for your server, 2) perhaps configuration details / examples for the FT2232D, and 3) HDL for the fpga I/O to make this all work. I'm very curious about exactly how this communications path works. A forum link, or links, would be fine if you've already documented it. Thanks in advance. dandreat

Hi, Jack; I wonder if you might share 1) source for your server, 2) perhaps configuration details / examples for the FT2232D, and 3) HDL for the fpga I/O to make this all work. I'm very curious about exactly how this communications path works. A forum link, or links, would be fine if you've already documented it. Thanks in advance. dandreat