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  1. julien

    FPGA in asynchronous mode

    Hi, @offroad: That's the kind of things I wanted to know. Thanks a lot Now that I know a little bit more about the vocabulary and its meaning, I can say that the schemes I want to implement are pure combinational logic. I do not reject synchronous designs, I perfectly understand the pros and (the few) cons, I just want to build a small experiment Best, Julien
  2. julien

    FPGA in asynchronous mode

    Hi That's exactly what I want to do Sorry for not yet knowing the technical language and how all the FPGAs related stuffs. I just seen David's PhD defence 2 or 3 weeks ago, I found all this work really interesting, read the papers (these guys are physicists and may have not used the accurate technical language), planed to buy a card and redo the experiments myself last week, and I am now learning Verilog and lot's of background knowledge about how FPGAs work. So, Is there any specific things to do in the programming stage or compiling stage in order not to use the flip-flops and clock? I may also have to change the title of the topic, no?
  3. julien

    FPGA in asynchronous mode

    Hi, Thanks for the answers. @hamster: I have already taken a quick look at this project. I have not yet asked any question there... @Jack: I understand why asynchronous mode is usually disregarded. The scheme I want to implement is not that advanced but requires asynchronous mode. By the way, the schemes I am interested in are networks of "autonomous boolean oscillators" (see pictures in http://arxiv.org/pdf/1302.1375.pdf), where one oscillator is usually one inverter gate with time-delay feedback and time-delay feedback is just an even number of inverter gates to just slow the signal. Oscillators are coupled through OR, NAND, XOR or XNOR gates. It has been shown (both by theory and experiments, once again refer to previous link) that these kind of schemes can generate chaotic dynamics, synchronization. But you need asynchronous mode for that... The authors of the paper are wiling to share the code (Verilog), they used a Altera Cyclone IV EP4CE115F29C7N board to implement their schemes. I am planning to implement the same kind of experiments on one of the papilio board. That is why I asked about asynchronous mode Best, Julien
  4. Hi, I may have not dug enough into the Papilo FPGA cards documentation yet, so I am asking here: What about removing the clock? to work in asynchronous mode. How difficult is this with the different cards (I am yet considering buying the Papilio Pro, but answers for the other cards are also welcomed). Does anyone already did it? For information, I am trying to reproduce some results of Dr. David Rosin from Duke University / Technische √ľniversit√§t Berlin (http://fds.duke.edu/db/aas/Physics/researchers/dpr12), so I really need this asynchronous mode. And I would not go for proprietary devices Best, Julien