I've got a very simple design running on a PapilioOne 500K, implementing multiple quadrature encoder interfaces and PWMs. It all works flawlessly in simulation, but in the actual hardware it is flaky. For a given build, the flakiness will manifest in a very consistent manner. I can make some inane change to the logic, and the flakiness will move to a completely different part of the circuit. I've examined the generated gate-level logic, and it is exactly what I would expect (I've been doing chip design for 25+ years). At first, I thought I just got a bad FPGA, so I got a replacement board, but I get the exact same results. I can do synthesis at 2X the target clock rate, and still have LOTS of margin on all paths. As an example, I've had two quadrature encoders and two PWMs operating for over a week now without a single problem. Yesterday, I added two more PWMs, and now just one of the quadrature encoder interfaces is working - it's completely ignoring the encoder inputs - or, likely more correctly, I can no longer read the encoder counter. But, that same interface has worked perfectly for the last week and I have made NO changes to the RTL, except adding the two additional PWMs. All the PWMs work fine, as does the other identical encoder interface. I'm quite confident the RTL is correct, and it ALWAYS simulates correctly, so about all I can figure is I am doing something wrong in the configuration of the tools, and it's perhaps not building for the right chip or something like that. I have it configured for a xc3s500e-4vq100, and 32MHz clock at LOC P89. The clock is defined in the UCF file as: NET "CLK" TNM_NET = CLK;TIMESPEC TS_CLKSPEC = PERIOD "CLK" 31.25ns HIGH 15.125 ns; That is correct, right? Is there anything else I could be doing wrong that could explain this odd behavior? I did have one helluva time getting the Xilinx tools to install properly, as I'm running Win 8.1, but except for this problem, they now seem to be working fine. Regards, Ray L.