Wendo

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About Wendo

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  1. Jack Any chance you could link to the actual 7 seg display part used on the LogicStart boards? Ideally with an RS/E14/Digikey part number? After some digging I think it's just one of these Just want to make sure if/when I burn mine out Also, on a semi related note, from what I can tell the central colon on the disply isn't actually connected on the LogicStart board, is that correct? Thanks
  2. Just to close this off, it was because I hadn't added an empty wishbone slot to my unconnected Wishbone 14 slot
  3. So, oddly, even though there are errors reported from the "Check schematic" it does actually build without errors and I end up with a bit file.... very odd
  4. Hi Everyone I have a Papilio on the way and am trying to familiarise myself with the ISE program which is proving to be... interesting Anyway, I figured I would follow the serial port example outlined here and try and work through it to at least get a bit file however the 1.6 schematic has GPIO_Wing ports created which appear to cause errors when I run "Check Schematic" if I try to connect the RX/TX pins directly to the WING_BL pins. I'm guessing I need to feed the RX and TX pins in through these new GPIO_Wing symbols but have no idea how to do that as the symbols don't appear to have any way to connect to them. The other thing it may be is that I have nothing connected to Wingslot 14, I only have 8 serials ports added and have no need for the 9th, and shouldn't I be able to leave the wishbone port empty? Based on the XLXN numbers below it _appears_ like thats the problem as Wishbone 13 uses 432 and 433 It's probably something fairly simple to sort out but I'm pretty much lost at the moment, can someone point me in the right direction. The specific errors I'm seeing are: ERROR:DesignEntry:207 - Papilio_Pro_8_UART.sch Bus 'XLXN_430(61:0)' and its bus members must be connected to symbol pins or I/O markers.ERROR:DesignEntry:207 - Papilio_Pro_8_UART.sch Bus 'XLXN_431(33:0)' and its bus members must be connected to symbol pins or I/O markers. using the PSL_Papilio_Pro_LX9 project template ThanksDave