aford

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About aford

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  1. I think the rate would be variable, set at runtime. Would it be possible to lock the clock (or the output) to an external trigger? I need to clock the system against a drifted sine wave (for a doppler radar system). The string of bits would also be variable, loaded into RAM during a setup phase. My initial idea was to set up an I/O line that I'd pull low, then feed in the bit stream (loading into ram). Then when ready, I'd pull low a line to start the output stream.
  2. I need output a binary bit stream at a specified rate. I need to drive TTL levels into a 50ohm system, but I figured any output conditioning can be accomplished externally. In essence, I have a string of bits (say 1Kb long) and I need to clock them out at a configurable rate (say anywhere from 5MHz up to the max achievable by the output pin). Would this be achievable? And any guesses/estimations as to what the realisitc max is, given internal clock limitations and the number of cycles required to move the data to the pin? Thanks a lot!
  3. Hello, I'm not familiar with FPGA development, so please bear with me if this isn't the right question to ask. Background: I'm trying to build a system to output PNCode that is pregenerated (to best suit task). In essense I need a whopping big shift register (the max code we use now is 128Kb long) that I can clock accurately and shift out at a predetermined rate. My question is, what's the fastest rate I can achieve using a Papilio? I'd like to flip the output pin at something close to 50MHz ( or as fast as possible really). I understand that the XTAL is 32MHz, and that I can use the internal clock managers to generate higher rate clocks, but how fast can I drive it, and how fast can I realistically drive a GPIO pin? Thanks, and my appologies if this is a stupid question.