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About Nadav

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  1. some updates needed

    it is in I also use windows 10 64b , the 2.12.28 version worked for me (first option) good luck!
  2. some updates needed

    ok, issue resolved! I forgot to install the FTDI driver
  3. some updates needed

    oops, my bad, I actually see two new COM ports when connecting Papilio, (see image) Now, the next obstacle is that the *.bit file of the project not getting the papilio icon, and when I try to give papilio the path for this file and burn the FPGA, nothing happens..
  4. some updates needed

    Hi Thomas, Thanks for your reply. I have downloaded the latest I found in the papilio website: "Papilio-Loader-V2.8" I see that it is an application ready to use, not installing anything, just opens JAVA gui. in device manager I don't see the Papilio as COM port... I suspect the Jungo win-driver, it is being installed within the XILINX web-pack, is it good for Windows10? Thanks, Nadav
  5. Hi Guys, 3.5 years ago when I was between jobs, I purchased the papilio one + logic wing and tough myself VHDL basics. it was good enough for me to get two job offers! Than I started the new logic design engineer job and put it aside. that job was (and still is) about high level synthesis - writing CPP code that later compiles and generates verilog code. So not much coding in HDL was done by me for the last 3 years. That brings me to my point: Now that I want to take of the rust and code some HDL (this time I aim for verilog) in my free time, I discover that it is not working in the latest environments: - windows 10 (64b) with ISE --> this I overcome(I think) from older thread reading -windows 10 (64b) with Papilio loader - looks like the application is not talking with the USB driver, or maybe it is the USB driver (jungo windriver?) which is not updated. I think that for me and for new people who would like to get to FPGA (or HDL learning) some documentation\scripting updates are needed Thanks, Nadav
  6. switch debounce

    Thanks a lot guys! you have really helped me a lot
  7. switch debounce

    Hi all, I am trying to solve the switch debounce problem in Hamster's book, chapter 17. Hamster suggestion is to solve it using some code lines in the FSM. My guess is that I need to ignore returning to previous state cases, for example if I'm moving from "00000001" state to "00000011"; when in "00000011", I will do nothing for the input "00000001", which can be a switch bounce. I haven't tested it yet, but it sounds sloppy, mostly because it doesn't pay attention to the amount of time of the bouncing, Is this the solution? I found on the web some switch debonce modules in vhdl which involve counter, but they where a lot harder to implement... can anyone share his solution or suggest what is the best way to deal with switch bounce with the tools acquired up to chapter 17? Thanks, Nadav
  8. Thanks offroad, so you are saying that in order to generate the signals requested(sin, square, saw, ramp) I should artificially create them and wrap them all in a 1024 rows ROM? I was hoping that signals should be a result of some DSP operation on the sine wave... Nadav
  9. Hi all, I am using papilio one + megawing in order to learn VHDL and logic design, in my free time. My question is about chapter 16's challenges, I don't think I fully understand the theory in the third line on page 74: "If you connect the two high address bits on RAM to switches you can have four different waveforms, each with 256 samples per cycle, possibly allow you to generate Square, Saw, Ramp and Sine waves from one project." I want to add that I am familiar with signal processing but I don't understand the method here. In my code I am using 8bit ROM with 1024 samples. values are of a full cycle of sine wave (so the first and the last equals 128, but values are between 28 and 228). If I will connect the two high address bits to switches I will only sweep on a quarter of a cycle for each switches combination, how's that giving me a square? or a saw? I tried it, even though I did'nt understand it, but for all the switches configuration the signal sounds the same... I will appreciate some help here Thanks:)
  10. thanks a lot!!!! Now I got it working!
  11. hi Guys. I am trying to solve the last challenge in chapter 10 (the binary counter) from hamster's book. I came up with the following code but it doesn't work so good: ------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity binary_up_counter is Port ( switches : in STD_LOGIC_VECTOR(7 downto 0); LEDs : out STD_LOGIC_VECTOR(7 downto 0); clk : in STD_LOGIC ); end binary_up_counter; architecture Behavioral of binary_up_counter is signal counter : STD_LOGIC_VECTOR(29 downto 0) := (others => '0'); signal sec_counter : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); begin clk_proc: process(clk) begin if rising_edge(clk) then counter <= counter+1; if (counter = 32000000) then if switches(0) = '1' then sec_counter <= sec_counter+1; counter <= "000000000000000000000000000000"; else sec_counter <= sec_counter; end if; end if; if switches(1) = '1' then sec_counter <= "00000000"; end if; end if; end process; LEDs <= sec_counter(7 downto 0); end Behavioral; ------------------------------------------------------------------ The counting starts only ~10 seconds after the time it should. should I have try a different design with the switches inside the sensitivity list? has anyone solved it befor? Thanks Nadav
  12. Hi Guys, I am new to the FPGA world. I am planning to get the Papilio ONE board with LogicStart MegaWing for FPGA and Verilog learning. My question is about the ADC chip on this wing. I understand that SPARTAN FPGA family doesn't come with analog IOs, so an external ADC was used, controlled by SPI protocol. Now lets say I want to play with this option,I guess that I need some kind of Verilog code in order to implement the SPI protocol into the FPGA, am I right? Is there an exsisting block I can use? I have looked for information about it, but all I found is stuff related to the ZAP IDE, while I want to use papilio as an FPGA development platform. Thanks:) Nadav