Hugo Sereno Ferreira

Members
  • Content count

    6
  • Joined

  • Last visited

Posts posted by Hugo Sereno Ferreira


  1. The idea of having ZAP to act as a central IDE to those schematics is *genial*. Well done, sir!

     

    I'm having some difficulties in opening the Bench Sump Logic Analyser in ISE though:

     

    ERROR: Failed to load symbols for C:\Papilio-Schematic-Library-1.6\examples\Benchy_Sump_LogicAnalyzer\Papilio_Pro.sch no netlist will be generatedERROR: Could not find symbol "Papilio_Wing_Pinout"ERROR: Could not find symbol "Wing_GPIO"ERROR: Could not find symbol "Wishbone_Empty_Slot"ERROR: Could not find symbol "COMM_zpuino_wb_UART"ERROR: Could not find symbol "ZPUino_Papilio_Pro_V1"ERROR: Could not find symbol "BENCHY_sa_SumpBlaze_LogicAnalyzer8"

    In the tutorial page you mention a base project, but it seems the information is already out-of-date in the 1.6 schematic library.


  2. I am attempting to convert the Logic Analyser to work on a Papilio Pro. Attached are my best efforts so far; ISE fails to build at some point with a cryptic error message:

     

    Optimizing unit <BRAM6k8bit> ...WARNING:Xst:2677 - Node <Inst_core/Inst_sampler/ready50> of sequential type is unconnected in block <Logic_Sniffer>.INTERNAL_ERROR:Xst:cmain.c:3423:1.29 -  Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.  

    Thoughts?

    VHDL_Core.zip