Hugo Sereno Ferreira

Actually, I don't have that option in the menu :-\ I'm using ISE Webpack 14.6 (free version).

The idea of having ZAP to act as a central IDE to those schematics is *genial*. Well done, sir! I'm having some difficulties in opening the Bench Sump Logic Analyser in ISE though: ERROR: Failed to load symbols for C:\Papilio-Schematic-Library-1.6\examples\Benchy_Sump_LogicAnalyzer\Papilio_Pro.sch no netlist will be generatedERROR: Could not find symbol "Papilio_Wing_Pinout"ERROR: Could not find symbol "Wing_GPIO"ERROR: Could not find symbol "Wishbone_Empty_Slot"ERROR: Could not find symbol "COMM_zpuino_wb_UART"ERROR: Could not find symbol "ZPUino_Papilio_Pro_V1"ERROR: Could not find symbol "BENCHY_sa_SumpBlaze_LogicAnalyzer8"In the tutorial page you mention a base project, but it seems the information is already out-of-date in the 1.6 schematic library.

Well, now I feel a little stupid to find out that this project is already available as a sketch in the new ZPUino IDE :-)

Well... almost... it seems that communications are working, since the software makes sense of the protocol (capture times also match). But, no matter what I connect the ports into, they always return the same result (in attach). I also attach the latest project. VHDL_Core.zip

Now that's strange... The error disappeared once I booted into Windows (was running ISE on a OSX with Wine). I'll let you know if I was successful in running the design.

I am attempting to convert the Logic Analyser to work on a Papilio Pro. Attached are my best efforts so far; ISE fails to build at some point with a cryptic error message: Optimizing unit <BRAM6k8bit> ...WARNING:Xst:2677 - Node <Inst_core/Inst_sampler/ready50> of sequential type is unconnected in block <Logic_Sniffer>.INTERNAL_ERROR:Xst:cmain.c:3423:1.29 - Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support. Thoughts? VHDL_Core.zip