aaremnair@gmail.com

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About aaremnair@gmail.com

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  1. aaremnair@gmail.com

    Looking for VHDL Code for Quickstart-Papilio_One_500K-v1.5.bit

    Thanks to both Jack and MicroN8. Finally I have my first VHDL program executing (using Switch_0 to control LED_0:-) What worked was the configuration in the file BPM7003-Papilio-One-LogicStart-MegaWing-general_1.2b.ucf. Thanks Jack for the suggestion to look at the bunch of ucf files; also the tip about LED_0 <= '0'. Regards RM
  2. Hi, I am working with the Papilio one and the Logicstart wing. I am trying to follow the e-book "Introducing the Spartan 3E FPGA and VHDL" by Mike Field. I cannot get past the first project (chapter 6). I have modified the constraint file to: #Constraints for Papilio 1NET Switch_0 LOC = "P91" | IOSTANDARD = LVTTL;NET Switch_1 LOC = "P92" | IOSTANDARD = LVTTL;NET LED_0 LOC = "P5" | IOSTANDARD = LVTTL;NET LED_1 LOC = "P9" | IOSTANDARD = LVTTL; The LEDs do not respond to any of the switches. The LEDs are all off. All the segments of 7-segment display are lit. Quickstart-Papilio_One_500K-v1.5.bit works as expected. I suspect that there could be change in the mapping of the FPGA pins to the LEDs, switches, and 7-segments. If I could get the source for Quickstart-Papilio_One_500K-v1.5.bit, I could check if there is a problem with the mapping. Where could I get the VHDL source? Thanks, RM