DanC

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About DanC

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  1. DanC

    The next generation Papilio - help me shape it.

    Thanks Jack for considering this. In fact I've been waiting for this PFGA board, which is Arduino-format compatible. I have designed many boards that have an Arduino Mega as controller plug-in, but the ATmega is getting to limited (speed etc.). So the new Papilio DUO would be excellent for me and my partner Albert (Alvie knows him also) to start testing and using in June. Hi Alvie, yes I'm doing fine, thanks. The purpose is to use the DUO with ZPUino, AND as Arduino connector format. Our project is more or less waiting for this, though I have to admit that this will involve a big learning curve for what we intend to do with the DUO. regards, -Dan
  2. DanC

    The next generation Papilio - help me shape it.

    Hi Jack, this is excellent news! I have a new project running, which is related to PLL control of some plasma lamps and ferrite reactors. It would really help if I could urgently get hold off 2 to 3 Papilio DUO. So I will closely follow the Kickstarter project. thanks -Dan
  3. DanC

    Papilio DUO - Prototype builds and testing!

    Hi Jack, How are you getting on with the DUO? I hope you've made good progress and the board works fine. Any timing yet when you could sell the boards? -Dan
  4. DanC

    Papilio DUO - Prototype builds and testing!

    Hi Jack, Any news? It's been a while since we heard from you on the DUO. best, -Dan
  5. DanC

    The next generation Papilio - help me shape it.

    Hey Jack, If possible, you can count me in for prototype 'playing'. Do you have already a cost in mind for the board? -Dan
  6. DanC

    The next generation Papilio - help me shape it.

    Hi Jack, that's great! I'm eager to see the finished board When can we put pre-orders? -Dan
  7. DanC

    The next generation Papilio - help me shape it.

    retrying with the table: PCB connector pin AVR pin on AVR pin on on Papilio DUO Leonardo Papilio DUO 13 PC7 PB1 12 PD6 PB3 11 PB7 PB2 10 PB6 PB0 9 PB5 PB7 8 PB4 PD0 7 PE6 PD1 6 PD7 PD4 5 PC6 PD6 4 PD4 PD7 3 PD0 PB4 2 PD1 PB5 1/TX0 PD3 PD3 0/RX0 PD2 PD2 14 - PB6 15 - PC6 16 - PC7 A0 PF7 PF0 A1 PF6 PF1 A2 PF5 PF4 A3 PF4 PF5 A4 PF1 PF6 A5 PF0 PF7 led PB0 PB1
  8. DanC

    The next generation Papilio - help me shape it.

    Hi Jack, I did a check on the ATmega32U4 pins allocated on the Leonardo versus the Papilio DUO, and most pins are differently connected. I don't know if this is intentionally or not. If you would like to preserve the Leonardo functionality, maybe better to relocate the pins. The analog pins are easy, as they are just in reverse direction. The digital/PWM/led pins might need a check to maintain the JTAG connections. -Dan PCB connector pin on Papilio DUO AVR pin on Leonardo AVR pin on Papilio DUO 13 PC7 PB1 12 PD6 PB3 11 PB7 PB2 10 PB6 PB0 9 PB5 PB7 8 PB4 PD0 7 PE6 PD1 6 PD7 PD4 5 PC6 PD6 4 PD4 PD7 3 PD0 PB4 2 PD1 PB5 1/TX0 PD3 PD3 0/RX0 PD2 PD2 14 - PB6 15 - PC6 16 - PC7 A0 PF7 PF0 A1 PF6 PF1 A2 PF5 PF4 A3 PF4 PF5 A4 PF1 PF6 A5 PF0 PF7 led PB0 PB1
  9. DanC

    The next generation Papilio - help me shape it.

    red and white (or the reverse also looks good: white & red)
  10. DanC

    The next generation Papilio - help me shape it.

    I agree, black is too dominant. I like the red as well. Hey Jack, the name Papilio DUO sounds good. I resembles the Arduino DUE naming concept (different meaning though between DUE and DUO), where you make a major upgrade step. Secondly, you point to the fact that there are 2 processing chips: FPGA and ATmega. some remarks on the PCB layout: - the ground traces on the LTC3419 are too weak (TOP layer) - pin 5 & 6. Make a small GND polygon around those pins (and cap C3), directly connected to GND layer with via. - same for the main power pin of the LTC3419 - make trace as thick as possible up to pin 7. - all 5V power traces on entire PCB should be wider - some atmega ADC pins are shared with digital pins; this might cause ADC noise issues. - I wonder if the FPGA has enough decoupling caps. The datasheet recommends 17. VCC-int and VCC-aux is ok. VCC0_1 VCC0_3 is ok (both banks have each 2 caps) VCC0_0 VCC0_2 only have 1 cap each. I would add a cap on pin 63 and one on pin 122 - at the top right connector, you have (from top to bottom) 2x 3V3 and 2x GND. The GND might conflict with shields as this is the place for the +V. Would it make sense to switch around the 3V3 & GND? - can you add IOREF pin on connector (next to RST pin) (you would need to move R31). IOREF is an important reference for shields. Connect 3V3 to this. - some traces on layer "Route 3" can be more "fluent" and straight For the rest, VERY NICE DESIGN !!
  11. DanC

    The next generation Papilio - help me shape it.

    Hi all, Ok now it works with my Eagle v6.4 If I download the files .brd & .sch 'as-is', they don't work - the content is rubbish. I need to view the files in 'raw', copy/paste to text editor, and save corrrespondingly to .brd or .sch. I never had to do it this way before, so I don't understand what I'm doing wrong. Anyway, I can read the files now. thanks, -Dan PS: I don't think there is a discussion about Eagle or not for the Papilio, for me Eagle is a de-facto given.
  12. DanC

    The next generation Papilio - help me shape it.

    Jack, I have Eagle 6.4.0, and can't read the files I have no immediate plans to buy the upgrade to 6.5.0. -Dan
  13. DanC

    The next generation Papilio - help me shape it.

    Hi Jack, I just tried to have a look at the files on Github, but the .sch and .brd files do not appear to be Eagle format. The content is different. -Dan
  14. DanC

    The next generation Papilio - help me shape it.

    Hi, there are of course pros and cons to any format, including the Arduino. There are sooooo many formats out there. Every product has its own format and size. There is no standard, and interfacing those is always making different boards. The nice thing about Arduino is that it is to some extend a de-facto standard. It's better to have something imperfect, rather than having nothing. The 3.3V or 5V is a false problem, as that problem is there for any of the other boards/formats as well. And since there is layout v3, pin IOref is used todetermine the voltage used. I use that successfully with several self-developed high-end shields. It's not about having the old Arduino-shields being compatible with this FPGA board, but the huge potential for new shield development. I think Jack has perfectly understood this in terms of marketability. best, -Dan
  15. DanC

    The next generation Papilio - help me shape it.

    Jack, Re the auto-reset, yes I was referring to the other boards, like the Arduino-Mega board I used to work with a lot. Indeed the Leonardo is different, with reset trigger at 1200 baud and bootloader 8' wait, where alternatively the reset button can be pushed. Given you are using a 2nd USB port for the Atmega32u4 (which is great), the programming could also happen that way, IF the Arduino bootloader is installed. The ICSP pins are 9, 10, 11, 13 Dan