camera_boy

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  1. camera_boy

    Creating a Clock Output from Papilio

    So a quick update, last night I probed the 32Mhz oscillator directly with my scope and the waveform was perfect square at 32MHz, so the problem is not with the scope or probe. I still think it's related to the stray parasitic effect from the board/IO/wing at such frequency or some IO buffer related issue in my design. If anyone has wants to do a quick experiment to confirm, that would be cool!
  2. camera_boy

    Creating a Clock Output from Papilio

    mkarlsson- I think you've nailed right on, I'm using a 200MHz scope and that may be the cause. I'll check by probing the oscillator directly on the papilio when I get home tonight. The article you provided was also really helpful in understanding. Thanks
  3. camera_boy

    Creating a Clock Output from Papilio

    Thanks for everyone's reply, yes I agree it must be the reactance causing the distortion. I've tried other pins and using TTL as suggested by Tb_ and results were similar. The scope may definitely have some effect too. I was able to drop the frequency to 16Mhz and my module (an image sensor) was still able to function correctly, so I will leave as is and will substitute with a real oscillator later on. Thanks for all the feedback.
  4. camera_boy

    Creating a Clock Output from Papilio

    Alex- It's not exactly the ringing effect, its more of a clock degradation, as if there's some large parasitic on the output, or a large RC on the load. Almost seems like the drive output buffer cannot drive the load fast enough. When I lower the frequency, it is much more square. Similar to this (google picture, I can get a shot this weekend) but actually even worse at 24Mhz. Hamster- I am using ODDR2 to forward the clock, here is my verilog: ODDR2 #( .DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" .SRTYPE ("SYNC") // Specifies "SYNC" or "ASYNC" set/reset) ODDR2_inst ( .Q (clk_out), // 1-bit DDR output data .C0 (dcm_output_clk), // 1-bit clock input .C1 (~dcm_output_clk), // 1-bit clock input .CE (1'b1), // 1-bit clock enable input .D0 (1'b1), // 1-bit data input (associated with C0) .D1 (1'b0), // 1-bit data input (associated with C1) .R (1'b0), // 1-bit reset input .S (1'b0) ); // 1-bit set inputOBUF #( .DRIVE(12), .IOSTANDARD("LVCMOS33"), .SLEW("FAST")) OBUF_inst ( .O(C[9]), .I(clk_out));
  5. My second newbie question, hopefully someone can help me and I'll be forever grateful. I'm using my recently purchased Papilio one 500k to create a 24MHz clock output to feed into a different chip/module. Why am I doing this? Because I bought the wrong oscillator for my other module and I thought hooking it up on the fpga would a quick temp solution. The design is super simple, just the regular 32Mhz clk in, to a DCM which modulate to 24Mhz, then to ODDR2 which drives an OBUF on one of the IO pins. The output pin is set as LVCMOS33 in my ucf and the OBUF driving it is also LVCMOS33 standard. However, when I measure the output on the board with an oscilloscope, the waveforms are really distorted but correct frequency. As if there's too much parasitic cap on the output. Going down to a much smaller freq around 8Mhz the waveforms are much more square. I've calibrated my probes over and over again. Are the "wings" or headers on the Papilio bad for driving such signal? Or do I need to change some iostandard or drive strength? Any advice suggestion? Thanks
  6. camera_boy

    Powering Down Papilio

    awesome thanks!
  7. I'm a newbie to FPGA, but I've worked on analog circuit design for many years at major corporations. I recently got a papilio board to play around with my 10 yr son and so you might see me here with some dumb questions, but please be patient as we're learning I want to know what's the correct way to power down the Papilio board even while a design is running. Is it safe to just yank the usb power? And what about FPGA's in general? Thanks