Chris_C

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Everything posted by Chris_C

  1. Chris_C

    JavaFX Logic toy

    While this isn't specifically fpga related I never the less think it a most cromulent way to play with logic networks... I'm considering making a none grid based more utiliterian logic simulator, now that I've proved that my state chage event system is suitable to simulate logic networks. While its really a toy I've been able to simulate adding 2, 4-bit values... You can read about it here http://chrisc.bedroomcoders.co.uk/logic-toy-a-logic-simulation-toy/ and grab the source here https://github.com/chriscamacho/LogicToy Enjoy !
  2. Allthough finding ISE an uphill struggle! (but I am getting there) a long term goal is to design and implement my own CPU design. I'm looking to make something small and simple yet also powerful I'd really value peoples thoughts if only just to help get another perspective here's my rough design so far... 1 16bit PC4 8bit registers R0 to R3No condition codes1-3 byte instruction codes IIII RaRb NNNN NNNNCCAAAA AAAA AAAA AAAAinstruction bits (IIII)Value (NNNN NNNN)Address (AAA...) where CC is present AAA... is a signed 14bit offset (should address the bus only be 14bit 16kb probably enough?)Ra Register R0 to R3Rb Register R0 to R3Rb16 value 0 or 2 representing 16bit register (0 = R0,R1) (2 = R2,R3)if an invalid Rb16 value of 1 or 3 is used then no 16 bit value is added tothe address (code 3 possible expansion ?)IIII Size Mnemonic Description0000 1 NOP spare ?0001 1 NAND Ra,Rb Ra=Ra NAND Rb0010 1 XOR Ra,Rb Ra=Ra XOR Rb0011 1 AND Ra,Rb Ra=Ra AND Rb0100 1 OR Ra,Rb Ra=Ra OR Rb0101 1 NOT Ra,Rb Ra=Ra NOT Rb0110 1 ADD Ra,Rb Ra=Ra AND Rb0111 1 SUB Ra,Rb Ra=Ra SUB Rb1000 1 SR Ra,Rb Ra shifted right Rb bits (only bottom 3 bits of Rb used)1001 1 SL Ra,Rb Ra shifted left Rb bits (only bottom 3 bits of Rb used)1010 1 HALT1011 2 SET Ra,NNNN Ra = immidiate 8bit value1100 3 PUT ( Rb16 + ADDRESS ) = Ra Ra is stored in address + Rb161101 3 GET Ra = ( Rb16 + ADDRESS ) Ra = contents of (address + Rb16)1110 3 JMPcc Ra,Rb, PC+(A14-A0 signed) where cc (top 2 bit of address) = eq ne gt lt1111 3 JMP Rb16 + ADDRESS PC = address + Rb16Virtual instructionsJMP ADDRESS is actually JMPeq R0,R0, ADDRESS
  3. thanks magnus, I'll take a look at the fpgaprog sources...
  4. Suppose I want my design to "load" data from the flash chip into sdram, at the moment I'd need a separate design to load data over serial (slow and painful even at 115200) save it temporarily in sdram and then write it into the flash If instead I could use the loader app with an offset I could upload the data to say +1mb in the flash at full USB speed AFAICT there is no parameter to specify where the data should start I suppose I could take my bit file pad it out at the end with zeros and add the data on the end but then thats going to make a very large file to upload...
  5. Looking at the code hamsters method does pad the bitfile and pload doesn't seem to have any options?
  6. Does this not mean I end up with a real massive file if I want something at say +2mb ? I'll have a look at pload though...
  7. yes, condition codes it is! I don't think life without at *least* a carry flag would be much fun! I'm still trying to work out if I really need a stack, while it would make call/return and even parameters easier - I'm still investigating alternatives.
  8. Allthough I could simulate some code which conditionally checked rising and falling edge, when it synthisised it spewed yet another cyptic error message statement is not synthesizable since it does not hold its value under NOT(clock-edge) I really need an error message to english translator! So I changed my logic about for the input it was complaining about and eliminated the falling edge check then it complained about the same thing but for a different input should I be using different processes for rising and falling edge, but then whats the best way to "communicate" between processes for example I can't really see how hardware could drive the same signal from two places? Assuming my logic really could only be done by detecting rising AND falling edge whats the best way to go about it... (incidently by changing my logic round I have a working module but I'm interested to learn about this for future pain with ISE)
  9. Obviously condition codes are useful, but for some reason I was attempting to see if they were really needed... I've never seen the point of fixed(immediate) offsets ? I did intially attempt a fixed size of all instructions but kinda seemed to end up with lots of wasted space for a bunch of instructions I'm trying to weigh up if a single return address is sufficient or if I need to implement a call stack I'll PM you with my email, it may be that we can help each other by batting ideas back and forth!
  10. Nice spot! I missed that! Ahem its a typo I meant Ra = NOT Rb or possibly Ra = NOT Ra 8 spare? I need to look again when I get home ! Thanks great feedback!
  11. These are good points especially subroutines and returns (can't see how to fit it into the current set) I decided to restrict it to an 8 bit bus initially (there may be son and even granson of this cpu!) to reduce complexity and also to ensure it doesn't take up lots of room... While I can see the attraction of stack machines (from a hardware designers point of view) I've never particularly enjoyed programming them, this will be a machine I'll code in assembler and don't have a need for a C compiler That said they are all good points especially subroutines / return, thank you very much for your constructive points. hmmm NOP and SPARE - I did leave myself wiggle room for call / return.... (but this would need a call stack)
  12. I decided that no one could possibly require more than 16kb of data ! This allowed me to tidy up some of my addressing ideas and I made invalid index register use clearer 1 16bit PC4 8bit registers R0 to R38 bit data bus14 bit address bus (16kb)No condition codes1-3 byte instruction codes IIII RaRb NNNN NNNNCCAA AAAA AAAA AAAAinstruction bits (IIII)Value (NNNN NNNN)Address (AAA...) top 2 bits are condition code if needed (eq,ne,gt,lt)Ra Register R0 to R3Rb Register R0 to R3Rb16 value 0 or 2 representing 16bit register (0 = R0,R1) (2 = R2,R3)rbX invalid Rb16 value of 1if an invalid Rb16 value (RbX) of 1 is used then no 16 bit value is added tothe address (code 3 possible expansion ?)IIII Size Mnemonic Description0000 1 NOP spare ?0001 1 NAND Ra,Rb Ra=Ra NAND Rb0010 1 XOR Ra,Rb Ra=Ra XOR Rb0011 1 AND Ra,Rb Ra=Ra AND Rb0100 1 OR Ra,Rb Ra=Ra OR Rb0101 1 NOT Ra,Rb Ra=Ra NOT Rb0110 1 ADD Ra,Rb Ra=Ra AND Rb0111 1 SUB Ra,Rb Ra=Ra SUB Rb1000 1 SR Ra,Rb Ra shifted right Rb bits (only bottom 3 bits of Rb used)1001 1 SL Ra,Rb Ra shifted left Rb bits (only bottom 3 bits of Rb used)1010 1 HALT1011 2 SET Ra,NNNN Ra = immidiate 8bit value1100 3 PUT ( Rb16 + ADDRESS ) , Ra Ra is stored in address + Rb161101 3 GET Ra , ( Rb16 + ADDRESS ) Ra = contents of (address + Rb16)1110 3 JMPcc Ra,Rb, ADDRESS where cc (top 2 bit of address) = eq ne gt lt1111 3 JMP Rb16 + ADDRESS PC = address + Rb16Virtual instructions provided byPUT (ADDRESS),Ra PUT ( RbX + ADDRESS ), RaGET Ra, (ADDRESS) GET Ra, ( RbX + ADDRESS )JMP ADDRESS JMP rbX, ADDRESS
  13. Chris_C

    Rising_edge and falling_edge

    @johnbeetem logisim http://www.cburch.com/logisim/ is simple even does rudimentary propagation delay and is fantastic getting the pure logic right! You can bash together a logic circuit to test you logic is OK in probably less then 10% of the time you could using schematic capture / simulation and its a lot more user friendly! @hamster I'm missing the point as i fail to see how that's better than a counter ? (the pulses must be at least 6 clocks apart?) Perhaps you'd like to make a separate post so others don't miss it?
  14. Chris_C

    Rising_edge and falling_edge

    My code as it stands now is working! I wanted to get a better understanding of rising / falling generally Add and end process and three endifs and throw something inside the ifs so they don't get optimised out and that should reproduce the error If you are particularly interested I could try to reintroduce the error into some fresh code One thing I find tiresome about the tools. (One of many things alas) is the fact it would simulate just fine, but not synthesise - what's the point of a simulation that doesn't actually simulate the limitations of the target device !
  15. Chris_C

    Rising_edge and falling_edge

    Unfortunately I rewrote the code to work round it but in one process DoPulse process(clk,pulsein) If rising_edge(clk) ... If falling_edge(clk) ... If falling_edge(pulsein) I can see why it would complain about falling clk but after its removal it complained about falling pulse in Is it possible to drive 2 buffers from say clk and detect rising on the output of one buffer and falling on the other ?
  16. Chris_C

    will the ide be cross platform

    Not owning windows I'm not sure if I missed anything with that zcpu arduino ide ( I think that's what it is?) However the ide for the duo looks a different class! Will it be available for Linux?
  17. After a fair break from almost everything electronic (thats what being a newly wed does for your "spare" time) I decided to get back into FPGA's Last time I got as far a VGA character generator in VHDL and concluded that the schematic route would probably suit me better! I does seem to bespite how aggravating ISE is ! (just don't get me started on BUS TAPS!!!!) anyhow I decided after getting the 32mhz clock downcounted to flash the led every 1/2 second, that I might look at input via USB my first instinct was to simply connect RX to TX which I did via a buffer - which works I get back what I send! (shocking!) however I get a warning that I'm not entirely comfortable with... WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp TX_PULLUP is set but the tri state is not configured. Now I do know what a pull up and tri state actually is BUT what I am wondering is how in the earth do you tell ISE what configuration you want for the tri state ( and why and whats needed for this circumstance) One the subject of USB serial, there is no clock?? if I want to read RX into an 8 bit buffer how do I know how long a bit is ?!
  18. Chris_C

    will the ide be cross platform

    I'd have thought using a cross platform framework would be easier.....
  19. At the moment I'm learning about schematic capture, which if nothing else is making me not do everything in one horrible giant cludge of a vhdl module ) I wanted to invert just one bit of a bus, yes I know I could very quickly write a tiny vhdl module and make a schematic symbol from it but bare with me that's not the point My issue is with bus tap - again! - never have I seen something so badly and unituitvly implemented and in 30+ years of messing with electronics and programming that really says something Now I have fairly well got the hang of getting a tap into or out of a bus (holy cow I might have to make a YouTube about it) , but what now seems problematic is a tap from one part of a bus to part of another bus without some intermediary. I ended up making a symbol from a separate schematic with two busses 7 buffers and 1inverter. Is there a better schematic method of effecting just 1 bit in a bus?
  20. I did see that page.... Alas clicking the YouTube links gets me to a 404 !
  21. I was afraid it would be asynchronous.... I do so prefer serial data thats clocked! (call me lazy!) I'll take a look for your recommended uart - thanks
  22. Yeah I gettcha, thanks, any idea about USB serial input timings?
  23. ok I've been round the houses tried a number of different things and badly need a break!!! scrMem:=scrMem + vCounter(3 downto 0);I'm trying here to add the lowest for bits of a logic vector to an integer variable - obviously this isn't the way to do it! and for further mirth enjoy this... if cdata(hCounter(2 downto 0) downto hCounter(2 downto 0)) thenI'm trying to test the nth bit of cdata (logic vector) where the value of n is the lowest 3 bits of a logic vector I'm so not groking the finer points of VHDL at the moment - nothing to do with the nature of fpga's I get that aspect of VHDL and circuit design isn't sequential programming thing - rather its the very awkward way it deals with values, bases and logic.... 4 bits, could be four individual bits, or a nibble, or a BCD digit even (just) signed or unsigned - but struth these 4 identical bits seem to move to a different county let alone post code should you have the timerity to look at the in a slightly different way for a picosecond.... honest I've enjoyed brainf__k programming more.... right I'm off for a nervous break down and a strong brownian motion generator without milk...
  24. Chris_C

    help! vhdl... melting... brain...

    I've found using verilog a lot easier than VHDL but I suspect its horses for courses this whole idea that fpga's are hard because they are a whole different paradigm is really over egged. anyone whose made even fairly rudimentary circuits using 74 series logic should be able to get their head round things quite quickly I still maintain the hardest thing about getting rudimentary fpga skills is VHDL