tmorkus

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About tmorkus

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  1. tmorkus

    IP core generation problem

    Hi Jack, I found much better workaroung for IP core generation under Linux - no need to disable ASY. I hope, that this may help somebody other as well. - don't use "New Source" from Design tab for IP core generator at all. Instead go directly to "Tools -> Core Generator " - select "File -> New Project", and set name to the project (or let the standard coregen.cgp) - then select "Project Options" to Spartan6, xc6slx9, tqg144, -2 - select the IP core from the menu list and generate them standard way, no need to disable ASY generation - close the "Core Generator" window - then in Design tab add a new source to the project select "Add source", select "ipcore_dir" and then select the generated IP core, "OK" - and that's all folks, everything seems to work correctly. If there are existing IP cores, there is no need to add new project, just add the IP core via "Tools -> Core Generator ", not from the Design tab. Also further changes to IP core (e.g.) add the *.coe has to be also done via "Tools -> Core Generator ". BTW: This is a great news about the ZAP IDE, hope, that the official release will be available soon Tomas.
  2. tmorkus

    IP core generation problem

    Hi Jack, I'll try the same VHDL code under Win7/64bit, but I dyslike Windows and try to avoid using them. Just for curiosity :-) I thought that the base of the ISE is the same under both OSes. BTW: I appreciate, that also your software is for Linux as well - most but the ZAP IDE. Tomas.
  3. tmorkus

    IP core generation problem

    I see, OK, I'll uncheck the option, I am learning VHDL only. May I have once more question regarding ISE? Which version of ISE you recommend to use for Papilio Pro? Thank you, Tomas
  4. tmorkus

    IP core generation problem

    Thank you Jack. And what about the ASY problem mentioned in the first post? Am I doing it correctly, or is there any/better way how to avoid this error? Tomas.
  5. tmorkus

    IP core generation problem

    Now I created the IP core different way: "Tools->Core Generator". There I changed "Project options" : unselect the "ASY Symbol File". Then I was able to renerate the block RAM and add them to my project. But when generation bit file: I get this error message: WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs (RAMB8BWER). 9K Block RAM initialization data, both user defined and default, may be incorrect and should not be used. For more information, please reference Xilinx Answer Record 39999. But the bit file is generated and seems to be working. Should I ignore this warning? Thanks, Tomas
  6. tmorkus

    IP core generation problem

    Hi, I am new there, I'm just learning using Papilio Pro and the Hamster's book, so please forgive me if this is some beginners mistake ;-) I have problems with generation Block Memory as described in the Chapter 15 of this book - I get following error message: ERROR:sim:938 - Error while preparing for IP customizationERROR:sim - Failed to initialize IP model.ERROR:sim:944 - Failed to generate ASY schematic symbol.ERROR:sim - Failed to generate 'memory'. Failed to initialise IP Model for ASY schematic symbol Using ISE 14.7 under Linux 64 bit (Ubuntu 12.04). I tried also ISE 14.4 before, but there were no IP cores for Spartan 6 xc6slx9-2tqg144. Please, can anybody help? Thank you. Tomas