bleedinggums

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Everything posted by bleedinggums

  1. bleedinggums

    ERROR:Place:1018

    hi everyone! i'm glad to say after some hours of hard work, i finally got my design running fine now! fpga rocks! the simulator is a godsend! one issue though. the connectors got loose after a few insertions. when i was debugging my design, some pins were not responding. i checked and checked and it turned out that the spring lock inside the connector couldn't get a tight secure fit any more. is there a way to rescue this connector? i would hate to desolder the row of pins. can i buy papilio one without the sockets installed? so that i could have my choice of sockets? thanks to all who commented on this thread. hey, thanks for even reading this thread! bg
  2. bleedinggums

    ERROR:Place:1018

    hi! i bought the papilio mainly because i want to use it in my product. one of my product requires a deserialiser. the fpga seems perfect for this application. i went for papilio as i wanted to use port c for the input data and use ports a and b to output data in parallel. however, i encountered some problems using it. first of all, when i want to create the design, i get this pesky error message. " ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /clock site pair." my signal consists of BitClock, Data and etc. the data will synchronise with BCLK. i wanted to use P98 as BitClock. naturally my program works on "rising_edge(BCLK)". but it seems i can't use P98 for this purpose. i tried a few other pins and it seems i keep on getting other errors related to my choice of pin for BitClock. any suggestion here? thx! bg ps: i scoped and i can't get any output at all. i suspect it's related to this 1018 error.
  3. bleedinggums

    ERROR:Place:1018

    hi jack yes, it's a good idea to start from a known base. i downloaded the bit file from the above link but still no cigar. i tried many things including uninstalled the loader and downloaded and installed the loader again, but still same results. i finally got it working when i set the loader to expert mode. seems like i need to select "erase", "write to" and "verify" when writing to spi flash for it to work properly. all this while i was using simple mode. this is strange isn't it? all i know is it works now. the downloaded program toggles even numbered leds and i could download my switches_led program. i'll try out my application and see how things go from here. thx again for the help. bg
  4. bleedinggums

    ERROR:Place:1018

    hi jack i don't need the bmm file? i program the bit file to spi flash, nothing happens. when i had the bmm file, i program both bit and bmm file to spi flash, the program managed to stay there and i was able to execute my led switches program after power off. where did i go wrong? bg
  5. bleedinggums

    ERROR:Place:1018

    oh no, i seemed to have goofed up again. now for some reasons, i could only generate the bit files but i can't generate the bmm file. how do i generate the bmm file? i looked around, everywhere it says xilinx should build it automatically but i don't see it. appreciate the help. thx! bg
  6. bleedinggums

    ERROR:Place:1018

    thank you! i finally tried again today. so i need to write both bit and bmm files to spi flash. it works now! thx! bg
  7. bleedinggums

    ERROR:Place:1018

    wait a minute! i tried the whole rigmarole again. i realised after writing to the fpga, the program works right away! but after it loses power (like i plug/unplug the usb cable), i seem to have lost everything. is this the reason? because previously i have taken out the unit and power it on again. uh oh, i must have done something wrong here! guess i have to program hex file instead? or i should ask, how do i store the program on the papilio one board so that the program could run every time it is powered up? bg
  8. bleedinggums

    ERROR:Place:1018

    hi guys what a day! i scoped the signals again, either way with earlier or later version of my program, i should get some signal as my simulation shows. still nothing. so i took a step back and since i have the logic start megawing, i tried out the led switches program using switch 0 and 1 (p3/4) to turn on/off led 0 and 1 (p16/17). guess what? nothing happened! so i suspect this is not an issue with my code. maybe it's in the programming process? or my pc? when we download the program to the fpga, it's just the bit file and nothing else right? i'm using windows 7, the 64bit ise project navigator. appreciate if anyone has any input on this. thx! bg
  9. bleedinggums

    ERROR:Place:1018

    hi jack thanks for your reply. err, could you speak in english please? i checked the synthesis report, it says summary: inferred 1 counter inferred 81 d-type flip flops inferred 1 comparator so i thought i'm good but as i scroll down the report, in the advanced hdl synthesis report section, i see # counters 1 5 bit down counter 1 # registers 81 flip flops 81 # comparators 1 5 bit comparator greater 1 # xors 1 1 bit xor2 1 but then i think i need flip flops in the design, since it's a simple deserialiser. my code is very simple as shown above, no? hi hamsters in my constraints file, all my signals are defined as NET BCLK LOC = "P91" | IOSTANDARD = LVTTL; i guess this is okay? thx! bg
  10. bleedinggums

    ERROR:Place:1018

    hi guys thanks to everyone who replied on this thread. the simulator is AWESOME!!! took me a while to get going, then only i realised the fun of it! most of the logic is what i want, which is nice but... how come i'm not getting any output? i'll try to scope the outputs again. thx again for the help! bg
  11. bleedinggums

    ERROR:Place:1018

    hi guys thanks for the comments. i checked out the pdf file and found that i could use pin 91 as it is also a GCLK pin. hardware wise, i just have to solder a jumper wire to it. awesome! now there is no more that pesky error message. however, i'm still not getting any output. i suspect it is my vhdl coding now. as this is just a deserializer, i'm wondering what could go wrong? it should be quite straightforward. sorry, obviously i'm not very good at this. appreciate if anyone could take a look at my code. thx! bg DAC.vhd
  12. bleedinggums

    ERROR:Place:1018

    hi alvie thx for replying. the signal is only 5 mhz. so it's not very fast. i don't understand what do you mean by choosing a GCLK input for my clock? how do i do this? i also don' know about adding the input clock buffer. sorry, first time using fpga here. i'm using papilio one 250k. bg