Corey Kosak

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About Corey Kosak

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  • Location Hoboken, NJ, USA
  1. Homebrew Cray-1A

    We live in exciting times! One issue might be that his project is using a 64-bit-wide data bus. The DUO's SRAM data bus is 8 bits right? Adapting to this cause this DUO-based Cray to run a tad slower.
  2. Homebrew Cray-1A

    Hm, really? I think the author is using a much larger FPGA.
  3. Homebrew Cray-1A

    I came across this project today and thought you folks on the forum might find it entertaining. Amazing what you can do with an FPGA http://www.chrisfenton.com/homebrew-cray-1a/
  4. My DUO arrived today

    I've been on the forum for 2 years, but quiet lately
  5. My DUO arrived today

    Can't wait to get started!!!!!
  6. LogicStart Shield for the Papilio DUO

    Hi hamster, What I gather from your reply is that there are two important principles for the LogicStart: that it be low cost and that it is very simple to program so that it supports learning for people who are new to FPGAs. I think both of these goals make perfect sense. Now, what I'm wondering is, is there scope for a board more advanced than LogicStart for people who are at the next step of their education. You could call such a board "LogicNextStep" Put another way, what do you see are the next steps for someone who has done the basic learning on a board like LogicStart and would like more advanced hardware to mess around with? Which of the below is most similar to your thinking? Users should get a breadboard and parts and wire up something themselves. Users should go buy a different FPGA trainer altogether--Papilio is strictly for beginners on a tight budget. Or... there is indeed scope for a more advanced (and more expensive) board like LogicNextStep. And maybe Papilio will have that some day.
  7. LogicStart Shield for the Papilio DUO

    Hi Jack, I'm don't know what the latest proposal is, so I'm not sure if these suggestions even make sense. I'll just list them anyway [What I want the most] Bring out some number of I/O pins on the LogicStart wing so I can still control my own hardware even when I'm using the wing. Are the RGB leds you're talking about intended to replace the 8 monochrome leds that currently lie above the switches? I kind of like that idea. Any potential for replacing the 7-segment LEDs with 14-segment so that alphanumerics can be displayed? [More speculative, but I'd personally enjoy this] What about a second VGA connector to be used as an input? Then a person could build little realtime video processing filters like deblurrers, edge detectors, chroma-keying, etc.
  8. Newbie project #3 - animated shapes

    No, I'm afraid I must disagree. The evidence I have shows that two-dimensional arrays work just fine (I even have a cite (somewhere) in the Xilinx manual saying they work fine). The problem is with generics. Specifically, in the below code, the two-dimensional array "data1" synthesizes perfectly well. But the problem is when I try to specify the type all on one line (see data2) and when I try to specify the dimensions generically (see data3). The former is a minor inconvenience; the latter is a pretty awkward blocker. I'm (pretty) sure that modern VHDL supports the data3 syntax (and can synthesize it) or something similar. The problem is this particular Xilinx toolchain we're using. Hence my question about alternative toolchains. This is the code. data1, a two-dimensional array, synthesizes just fine. data2 and data3 do not compile. library IEEE;use IEEE.STD_LOGIC_1164.ALL;package whatever is subtype myvec_t is std_logic_vector(7 downto 0); type sig_t is array(0 to 2) of myvec_t;end whatever;library IEEE;use IEEE.STD_LOGIC_1164.ALL;use work.whatever.all;entity Main is generic (n: positive := 3; w: positive := 8); port ( data1: sig_t; -- a 2D array. synthesizes just fine. --data2: array(0 to 2) of std_logic_vector(7 downto 0); -- does not compile --data3: array(0 to n-1) of std_logic_vector(w-1 downto 0); -- does not compile, alas clk: in std_logic );end Main;architecture Behavioral of Main isbeginend Behavioral;
  9. Newbie project #3 - animated shapes

    Here is one example that gets my goat. I can, with some verbosity, make a two-dimensional signal "sig" which is parameterized by n and w, but there's no way do the same for the input port "data" using the version of VHDL that we have. library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity Main is generic (n: positive := 3; w: positive := 8); port ( --Uncomment the below to see the error. --data: in array(0 to n-1) of std_logic_vector(w-1 downto 0); clk: in std_logic );end Main;architecture Behavioral of Main is subtype myvec_t is std_logic_vector(w-1 downto 0); type sig_t is array(0 to n-1) of myvec_t; signal sig: sig_t;beginend Behavioral;
  10. Newbie project #3 - animated shapes

    By the way, as I was building this project I started collecting a list of frustrations where I found myself blocked by the language. I was quite surprised to see that there are certain constructs allowed in modern VHDL that are not supported by our Xilinx compiler. In some cases these are just nice-to-haves, but in other cases the lack of these features really blocked me from writing my code the way I needed to. I'm happy to explain what I mean in detail, but as a top-level question I was wondering: are there more sophisticated toolchains available, and if so, would the existence of such toolchains influence your decision on which chip to use for the next Papilio?
  11. Newbie project #3 - animated shapes

    Wow, that worked great. I'm so glad to be rid of that ipcore_dir. And that .gitignore is priceless! What about the iseconfig directory? I don't see that in the .gitignore, but I'm thinking that directory is also unnecessary. What do you think? Also I seem to have inherited a new VGAClock.sym file (https://github.com/kosak/PapilioPro-AnimatedShapes/blob/master/source/VGAClock.sym ). Not sure what I did to get that. Maybe I fat-fingered something. Anyway, thanks!!
  12. Hi folks, I thought I'd share my third project with you all. I got sort of obsessed with the idea of driving the VGA protocol without any frame buffer memory backing the display (note 1) and I wanted to see how far I could get with such a design. I ended up with a cute little program that bounces a few geometric shapes around the screen and also does boundary and collision detection. There's a YouTube video here (http://youtu.be/ltEPILMaUMk) and the source code is here: https://github.com/kosak/PapilioPro-AnimatedShapes Feedback on the code is very welcome. I'm a newbie VHDL programmer and I find the language sort of frustrating so I sort of made up my own coding conventions and did some other hacks. I also agonized a lot about how modular such a design should be and how inter-module communication should work. In the process I've also generated a bunch of VHDL questions which I hope to post somewhere, if y'all don't mind. The first is hopefully an easy one: I used the IP Core generator to get a 25.175MHz pixel clock and it crapped out a huge number of files into my ipcore_dir. I'm sure most of those do not need to be checked into source control. Can you tell me which ones are supposed to be checked in? Thanks for looking at my demo! (note 1) mostly because I'm intimidated by the SDRAM :-) This post has been promoted to an article
  13. Hi folks, I thought I'd share my third project with you all. I got sort of obsessed with the idea of driving the VGA protocol without any frame buffer memory backing the display (note 1) and I wanted to see how far I could get with such a design. I ended up with a cute little program that bounces a few geometric shapes around the screen and also does boundary and collision detection. There's a YouTube video here (http://youtu.be/ltEPILMaUMk) and the source code is here: https://github.com/kosak/PapilioPro-AnimatedShapes Feedback on the code is very welcome. I'm a newbie VHDL programmer and I find the language sort of frustrating so I sort of made up my own coding conventions and did some other hacks. I also agonized a lot about how modular such a design should be and how inter-module communication should work. In the process I've also generated a bunch of VHDL questions which I hope to post somewhere, if y'all don't mind. The first is hopefully an easy one: I used the IP Core generator to get a 25.175MHz pixel clock and it crapped out a huge number of files into my ipcore_dir. I'm sure most of those do not need to be checked into source control. Can you tell me which ones are supposed to be checked in? Thanks for looking at my demo! (note 1) mostly because I'm intimidated by the SDRAM :-)
  14. Papilio DUO - Prototype builds and testing!

    Wow! Really exciting!! Can't wait!!!
  15. Hi folks, I thought I'd share my second project with you all. I just bought this book and got some more ideas from it. I ended up making a little 16-element register file and wrapping a "user interface" around it. I filmed a little video, and I've also attached the source files. As I was doing this I noticed that the switches on the Papilio were not laid out in the order I expected. switch(0) is the leftmost when I expected it to be the rightmost. This is not a big deal--I could have RTFM'ed--but then I started thinking about how I wanted to deal with that. I might have edited my constraints file but I wanted to leave it alone. Instead I went looking for a way to reverse a logic vector in my design. I expected something like this to work: user_addr <= megawing_switches(0 to 3);user_data <= megawing_switches(4 to 7);But that gave me the error "Line 30: Slice direction does not match type range direction." So I ended up doing this, but I felt a little dirty. rewire: for i in 0 to 3 generate user_addr(i) <= megawing_switches(3-i); user_data(i) <= megawing_switches(7-i);end generate rewire;Is that really the simplest way to reverse a vector? I had another fun weekend here. Thanks again for listening! source.zip