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Everything posted by maheshpalve

  1. maheshpalve

    DATA2MEM problem

    hello, i'm using papilio one 500k board for developing an 8-bit processor. The working was good so far and I came to know about data2mem tool thr google .... I'm trying to use this tool for many days now. It gives me an updated bit file which I verified by dumping into text file. But, apperantly the data is not being written to BRAM by the this new bit file, because the processor is not executing the new code in BRAM. When I initialize BRAM by .coe file, the code executes. So, no problem with BRAM!!! Only, the new bit file doesn't work!! any suggestions?????
  2. maheshpalve

    DATA2MEM problem

    The mem file content order is OK. For a .coe file placed, the initial dumpfile shows code from .coe file. After data2mem, it changes that code i.e. replaces it with .mem file content. Well, I don't know what the problem was! But, this time I used RAMB16_S18 primitive directly, to instantiate my ROM in top module, instead of the core-generator. Then re-synthesis, re-implementation . . . Again used data2mem. And wow, it worked!!! Maybe I was wrong somewhere in synthesizing memory from core generator or something else. Thanks for your fast replies hamster . . . - Mahesh
  3. maheshpalve

    DATA2MEM problem

    my .mem file is like: @0000 0C01 6800 FFFF 0C08 6800 FFFF 0000 and dump file shows: RAM data, Column 00, Row 00. Design instance "rom0/BU2/U0/blk_mem_generator/valid.cstr/ramloop[0].ram.r/s3_noinit.ram/spram.ram". 00000000: 0C 01 68 00 FF FF 0C 08 68 00 FF FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..h.....h....................... 00000020: 00 00 00 00 00 00 00 00 etc. etc. and when I upload the new bit-stream the processor executes nothing!! Is anything wrong with the .mem content? I even tried : @0000 0C016800FFFF0C086800FFFF0000 which gives same result in dump file. - Mahesh