fcharby

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About fcharby

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  1. fcharby

    Wishbone and SDRAM

    Can you give me a little bit more information on how to use the DMA wishbone of the ZPuino? Or possibly a quick example? Maybe there is documentation somewhere and I haven't found it...sorry if that's the case...if there is, just let me know where it is and I'll get working on this right away! Thanks for the input.
  2. fcharby

    Wishbone and SDRAM

    Actually, that would probably fit my needs as well, although we could say my goal was kind of a subset of the whole OLS thing. I have no objections taking on a bigger project if I can get a little help to put me on the right track. The problem right now is I don't have a thorough enough understanding of the wishbone platform to know what can and can't be done. My original question was to make sure that the SDRAM could be accessed separately from the ZPUino core so that the write speed doesn't get slowed down by code execution...kind of like the BRAM blocks inside the FPGA can have separate channels. Anyway, I'd be happy to help out any way I can and if working a little harder on this means I can add extra functionality to my project as well as share it with others, all the better! Thanks.
  3. fcharby

    Wishbone and SDRAM

    Hello all, I have read a lot of posts, a lot of documentation, watched videos and I am still a little confused. I have downloaded the ZPUino source code and gotten it to compile in ISE. I can load sketches, etc, etc...It is all very beautiful and amazing and I'd like to integrate it to my project so that I can add more features to it. What I am wondering now is how I can customize this to fit my needs. I want to monitor a data bus using pins on my FPGA and on a specific trigger, write the data to RAM. I have come to realize that using SDRAM is very complicated so I was hoping to add my logic bloc as a wishbone peripheral of some sort that is hooked to the same wishbone bus as the SDRAM so that the data is writable from my bloc and readable from my sketch code..... Is that even doable? If so, does anyone have any pointers to get me started? If not, other suggestions are appreciated! Also, my wording here might be confusing here, let me know if I need to clarify.... Thanks everyone (and many more thanks to alvieboy and hamster for the code, the documentation and much more).
  4. fcharby

    Capture data to SRAM and retrieve later

    Well, I ended up buying the board anyway with some wings and other components, it's not that expensive, plus it looks like a lot of fun. I'll figure out what I can and can't do with this type of board and then I'll see where that takes me... Hamster, I also downloaded your tutorial which I will follow along from beginning to end. This will be a great journey and I look forward to it! Thanks all for your help.
  5. fcharby

    Capture data to SRAM and retrieve later

    Yes, I was aware of the logic sniffer project but it has a few limitations that can't be circumvented such as the amount of samples that can be captured.... My problem requires another solution, I'll be more specific, one of the buses I currently want to monitor is between a microcontroller and a parallel memory. On this specific board, there is a lot of activity on the bus because there are other devices connected to it but all I care about is the memory and what is read or written to it, so my idea was to use a FPGA to do all the work instead of having my computer download a crazy amount of captures to analyse the content and figure out what is what. With a FPGA, I could passively monitor a bus and reconstruct the content of a memory somewhere inside the SDRAM or even the FPGA memory. I also need to a able to deal with memories of a few megabytes... I could leave my device alone for a few minutes and let it collect data while not having to worry about overflowing.... I don't know if that changes anything, I guess this is still doable. I appreciate all the tips you guys have given me so far. Thanks
  6. Hello, I have a experience with microcontrollers and embedded systems, but I am entirely new to the world of FPGAs. I have an idea for a project that I'd like to do and I think a FPGA is the way to go, although I can't confirm that the Papilio Pro is the right board for it. Basically, I want to monitor a bus of 30+ channels and capture data on a specific trigger, that data would be stored in RAM and retrieved later probably via the serial FTDI chip, which makes the most sense since it's already available on the board. Is anyone able to tell me if this project is feasible with the Papilio Pro? Thank you in advance.