kk_omnisys

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About kk_omnisys

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  1. Output files from compiler

    Hi All, I've been reading about the Arduino IDE on the web, particularly this article https://www.arduino.cc/en/Hacking/BuildProcess In the section "Build process" I found that the Arduino IDE puts the files generated from the sketches in a temporary folder \Documents and Settings\<USER>\Local Settings\Temp (on Windows) /tmp (on Mac and Linux) Since I am working on a non-gadget factory board (The Pipistrello 2.0) I have some special operations I need to do every once in a while which requires a copy of the output .bin file with the whole sketch. Wouldn't it be nice to have the compiler output files and binaries in a sub-directory of the designlab sketch file, like ./build or similar so that we don't have to cruise around the filesystem to find the binaries? I can imagine that one time or another you actually want to save the exact binary you programmed your device with and then it would simply be a matter of tarballing or zipping the folder? Best Regards Kalle Kempe
  2. Designlab and Pipistrello

    Hi All, Since I wrote the last entry in this thread I've been poking around with the boards and I've found out that I need to have a zpuinocode already present in the flash for the uploads to work in designlab. This is a bit of trouble if the .bit file from the Xilinx tools is switched out alot.. I do not know if there is something I'm missing, perhaps Alvie can fill in some info? Best Regards Kalle Kempe
  3. Designlab and Pipistrello

    Just found a solution. My guess is that the upload speed for papilio with sys clk of 96 MHz and the 100MHz is larger than the tolerance of standard UART. Uploading in designlab can be enabled by changing the upload speed. I found the line in Designlab\hardware\zpuino\zou20\platform.txt which describes the command issued to program the board tools.zpuinoprogrammer.upload.pattern="{path}/{cmd}" -s {upload.speed} -R {upload.verbose} {upload.memory} -d {serial.port} -b "{build.path}/{build.project_name}.bin" {upload.smallfs}The difference between my line in previous post is the port speed. So in designlab\hardware\zpuino\zpu20\boards.txt I created a section for the pipistrello: zpuino_pipistrello_lx45van.name=Pipistrello - ZPUinozpuino_pipistrello_lx45van.vid.0=0x0403zpuino_pipistrello_lx45van.pid.0=0x6010zpuino_pipistrello_lx45van.name.0=Pipistrello FPGAzpuino_pipistrello_lx45van.boardid=0xba011a00zpuino_pipistrello_lx45van.upload.protocol=zpuino-serialzpuino_pipistrello_lx45van.upload.maximum_size=8388608zpuino_pipistrello_lx45van.upload.size_sections=allzpuino_pipistrello_lx45van.upload.speed=115200zpuino_pipistrello_lx45van.upload.tool=zpuinoprogrammerzpuino_pipistrello_lx45van.build.f_cpu=96000000Lzpuino_pipistrello_lx45van.build.core=zpuinozpuino_pipistrello_lx45van.build.mcu=zpuzpuino_pipistrello_lx45van.build.toolchain=zpuzpuino_pipistrello_lx45van.build.board=ZPUINO_PIPISTRELLOzpuino_pipistrello_lx45van.build.extra_flags=-D__ZPUINO_PIPISTRELLO__ -DBOARD_ID=0xba011a00 -DBOARD_MEMORYSIZE=0x800000 -nostartfileszpuino_pipistrello_lx45van.build.extraSflags=-DBOARD_ID=0xba011a00zpuino_pipistrello_lx45van.build.mcu=zpuzpuino_pipistrello_lx45van.build.vid=0x0403zpuino_pipistrello_lx45van.build.pid=0x6010zpuino_pipistrello_lx45van.build.usb_product="Pipistrello FPGA"zpuino_pipistrello_lx45van.bitloader.tool=papilioprogzpuino_pipistrello_lx45van.bitloader.file=lx9/zpuino-1.0-PapilioPro-S6LX9-Vanilla-1.0.bitzpuino_pipistrello_lx45van.xise.file=circuit/PSL_Papilio_Pro_LX9.xisezpuino_pipistrello_lx45van.sch.file=circuit/Papilio_Pro.schzpuino_pipistrello_lx45van.pdf.file=circuit/schematic_papilio_pro.pdfzpuino_pipistrello_lx45van.bit.file=circuit/LX9/papilio_pro.bitzpuino_pipistrello_lx45van.logicanalyzer.file=logicanalyzers/LX9/papilio_pro.bitzpuino_pipistrello_lx45van.logicanalyzer.message="Channels 0-15 are connected to the B Wing and channels 16-31 are connected to the C Wing."Note that I changed the default upload.speed to 115200 Works a charm Best regards Kalle Kempe
  4. Designlab and Pipistrello

    I found that I can program the Zpuino code from the commandline C:\DesignLab-1.0.7\hardware\tools\zpu\bin>zpuinoprogrammer.exe -R -d com25 -b data.bin -v But that means that I have to compile the source, find the temporary path where the binary is and copy it to some place where the zpuino programmer executable is.. tedious Kalle Kempe
  5. Zpuino on the pipistrello

    Got it to work. The CPU had no Zpuino code to run in the flash. Got that running with the command line tools: papilio-prog.exe -b bscan_spi_lx45.bit -f pipistrello_top.bit -v -r -rAnd manually programming the Zpuino code: C:\DesignLab-1.0.7\hardware\tools\zpu\bin>zpuinoprogrammer.exe -R -d com25 -b data.bin -v
  6. Hi All! I've cloned the papilio loader app from Github and tried using it with the pipistrelloboard. I figured out that I can add the device id to the devlist.txt file. So far so good. I found that I can run the command-line app with a bscan_spi_XXXX.bit file to program my flash. even better! Looking over the sources for the java GUI I found that the devices it supports is hardcoded in papilioloader.java private File DetectJTAGchain() { File bscanBitFile = null; String[] scanJTAG; String[] scanJTAGOrig = {q_papilio_prog_exe, "-j"}; String[] scanJTAGID = {q_papilio_prog_exe, "-j", "-d", "\"" + pnlTarget.getBoardName() + "\""}; if (pnlTarget.getBoardName().isEmpty()) scanJTAG = scanJTAGOrig; else scanJTAG = scanJTAGID; execSynchronously(scanJTAG, programmerPath, true); //txtOutput.append("In DetectJTAG: " + deviceID); if (!deviceID.isEmpty()) { //txtOutput.append("In isEmpty: " + deviceID); if (deviceID.equals("XC3S250E")) bscanBitFile = new File(rootProgrammerPath, "bscan_spi_xc3s250e.bit"); else if (deviceID.equals("XC3S500E")) bscanBitFile = new File(rootProgrammerPath, "bscan_spi_xc3s500e.bit"); else if (deviceID.equals("XC3S100E")) bscanBitFile = new File(rootProgrammerPath, "bscan_spi_xc3s100e.bit"); else if (deviceID.equals("XC6SLX9")) bscanBitFile = new File(rootProgrammerPath, "bscan_spi_xc6slx9.bit"); else if (deviceID.equals("XC6SLX4")) bscanBitFile = new File(rootProgrammerPath, "bscan_spi_xc6slx4.bit"); } return bscanBitFile; }Can't this be more general, like having an extra column in devlist.txt? Best regards Kalle Kempe
  7. Zpuino on the pipistrello

    Hi! I am working on getting the Zpuino on my Pipistrello. I cloned the Zpuino repository from github yesterday and created a ISE project for the pipistrello using the files referenced in the pipistrello board directory .prj file. It runs through the synthesis, p&r and bit file generation fine after switching out the deltasigma entity for an empty wishbone device. Is there anything else that needs to be done for the .bit file to be correct? Best regards Kalle Kempe
  8. Papilio loader or MiniSprog?

    Hi! I am working to get my pipistrello up in a Designlab enviroment with the Zpuino. MiniSprog works to burn the .bit file in flash The papilio loader does not, anybody know what to do? I tried changing the devlist.txt to include the device code for the lx45 but that only lets me program the fpga directly, not flash. Best regards Kalle Kempe
  9. Designlab and Pipistrello

    Hi All, I'm working on a project with a Pipistrello 2.0 that I want to use with the Designlab. Presuming that I get the .bit file into the flash and FPGA I also want to upload code from the Designlab GUI. I see that the Designlab 1.0.7 has been streamlined for only papilio boards. I have started modifying some files around the designlab but so far I'm flying blind. Can someone help with instructions on how to enable Pipistrello in the Designlab GUI? Best regardsKalle Kempe
  10. spi.vhd error?

    Bump! Should I post this on GITHUB somehow so that it gets merged and so that Alvie or someone can fix the remaining trouble with the ZPUino?? Regards Kalle
  11. The next generation Papilio - help me shape it.

    Wow, I totally missed this topic over the last weeks.. lots of good stuff in here. I thought I'd just share some thoughts on the next design since I really like the platform and I'm thrilled to see it expand with new hardware We have used the Papilio Pro as a controller for a pretty cool project at the company I work for, but our bottleneck performance-wise is the transfer speed on the USB/UART My adventures with the FTDI FT2232H haven't exactly been a dawdle. Using the 245 FIFO mode to get the highest speed on the device uses 15 pins in my latest design. The timing requirements are a real headache (see page 27-28 in http://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT2232H.pdf ) and even on a Virtex-6 I had to work hard to make it work properly so I just want to make the point that somebody should try to check the timing requirements will be met. If we do not go for full routing for 245 FIFO mode of the FTDI chip, then what speed can we achieve with the device with MPSSE? From what I read on the FTDI website they say that the maximum UART bitrate is 12 Mbaud, but that is limited by the level shifters, which we do not use for FPGA < - > FTDI interface. Does anybody have any data on this, like from Pipistrello or something? I like the simplicity of using the UART mode since those drivers are easy to use on any operating system and most programming platforms (We use LABVIEW for example). I second Alvie's point on going to faster/bigger DDR RAM chips. For most users this will be completely transparent anyways. Regarding the Arduino footprint I see that it has its advantages. We recently started using the DUE in some of our projects and it's a big step up from the ATMEGA CPUs but still it lacks the versatility of the FPGA I really look for (like adding more SPI interfaces which is pretty easy with the Papilio). Furthermore the Wings already existing for the Papilio I do not think it is that hard to redo the design of the RetroCade wing to fit the new Papilio IF we don't have to make it compatible with the Arduino's. So on that point I think getting access to the already existing Shields for Arduino is a good thing. Here's another Idea I just thought of, could we make the Papilio dock as a shield on a Arduino MEGA/DUE or is that complete nonsense? I don't have anything against adding an Arduino on the board to get the Analog pins, I think it is a matter of convenience really since the Arduino is well debugged and tested. As long as it is secondary to the FPGA for the primary purpose of adding the analog pins (it would be nice if it were somehow reprogrammable as well when I think about it so that the programmer can customize the functionality, like taking samples at intervals and pushing them to the FPGA for example). Those are the things I could think about right now Kalle
  12. spi.vhd error?

    I fixed the spi.vhd (also modded the spiclk.vhd to get an extra clkfall at transfer start to push first bit to stream, changes below) to support both cpha modes, but now i get into trouble with ZAP. The flash is no longer recognized by ZAP, some help? ---- SPI interface-- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>-- -- Version: 1.0-- -- The FreeBSD license-- -- Redistribution and use in source and binary forms, with or without-- modification, are permitted provided that the following conditions-- are met:-- -- 1. Redistributions of source code must retain the above copyright-- notice, this list of conditions and the following disclaimer.-- 2. Redistributions in binary form must reproduce the above-- copyright notice, this list of conditions and the following-- disclaimer in the documentation and/or other materials-- provided with the distribution.-- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.-- --library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity spi is port ( clk : in std_logic; rst : in std_logic; din : in std_logic_vector(31 downto 0); dout : out std_logic_vector(31 downto 0); en : in std_logic; ready : out std_logic; transfersize: in std_logic_vector(1 downto 0); miso : in std_logic; mosi : out std_logic; clk_en : out std_logic; clkrise : in std_logic; clkfall : in std_logic; samprise : in std_logic -- Sample on rising edge, shift data on falling edge);end entity spi;architecture behave of spi issignal read_reg_q : std_logic_vector(31 downto 0);signal write_reg_q : std_logic_vector(31 downto 0); signal ready_q : std_logic;signal count : integer range 0 to 32;--signal count_val_q: integer range 0 to 32;signal sample_event : std_logic;signal do_shift : std_logic;signal ignore_sample_q : std_logic;begindout <= read_reg_q;process(samprise,clkrise,clkfall)begin sample_event <= '0'; if (clkfall = '1' and samprise = '0') then sample_event <= '1'; elsif (clkrise = '1' and samprise='1') then sample_event <= '1'; end if;end process;process(ready_q, en)begin ready <= ready_q;end process;process(ready_q, clkrise, clkfall, samprise, en)begin if ready_q = '0' and samprise = '0' and clkrise = '1' then do_shift <= '1'; elsif ready_q = '0' and samprise = '1' and clkfall = '1' then do_shift <= '1'; else do_shift<='0'; end if;end process;process(clk)begin if rising_edge(clk) then if do_shift = '1' then case transfersize is when "00" => MOSI <= write_reg_q(7); -- 8-bit write when "01" => MOSI <= write_reg_q(15); -- 16-bit write when "10" => MOSI <= write_reg_q(23); -- 24-bit write when "11" => MOSI <= write_reg_q(31); -- 32-bit write when others => NULL; end case; end if; end if;end process;process(ready_q, clkrise, clkfall, count)begin if ready_q = '1' then clk_en <= '0'; else if count/=0 then clk_en <= '1'; else if samprise = '0' then clk_en <= not clkrise; elsif samprise = '1' then clk_en <= not clkfall; end if; end if; end if;end process;process(clk)begin if rising_edge(clk) then if rst='1' then ready_q <= '1'; count <= 0; else if ready_q = '1' then if en = '1' then ready_q <= '0'; write_reg_q <= din(31 downto 0); ignore_sample_q <= not samprise; -- Shift the 32-bit register case transfersize is when "00" => count <= 8; when "01" => count <= 16; when "10" => count <= 24; when "11" => count <= 32; when others => NULL; end case; end if; else if count/=0 then if do_shift = '1' then count <= count - 1; end if; else if clkrise = '1' and ready_q = '0' and samprise = '0' then ready_q <= '1'; elsif clkfall = '1' and ready_q = '0' and samprise = '1' then ready_q <= '1'; end if; end if; end if; if ready_q = '0' and sample_event = '1' then ignore_sample_q <= '0'; if ignore_sample_q = '0' then write_reg_q(31 downto 0) <= write_reg_q(30 downto 0) & '0'; read_reg_q(31 downto 0) <= read_reg_q(30 downto 0) & MISO; end if; end if; end if; end if;end process;end behave;---- SPI Clock generator-- -- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>-- -- Version: 1.0-- -- The FreeBSD license-- -- Redistribution and use in source and binary forms, with or without-- modification, are permitted provided that the following conditions-- are met:-- -- 1. Redistributions of source code must retain the above copyright-- notice, this list of conditions and the following disclaimer.-- 2. Redistributions in binary form must reproduce the above-- copyright notice, this list of conditions and the following-- disclaimer in the documentation and/or other materials-- provided with the distribution.-- -- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.-- --library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity spiclkgen is port ( clk: in std_logic; rst: in std_logic; en: in std_logic; cpol: in std_logic; pres: in std_logic_vector(2 downto 0); clkrise: out std_logic; clkfall: out std_logic; spiclk: out std_logic );end entity spiclkgen;architecture behave of spiclkgen issignal running_q: std_logic;signal clkrise_i: std_logic;signal clkfall_i: std_logic;component prescaler is port ( clk: in std_logic; rst: in std_logic; prescale: in std_logic_vector(2 downto 0); event: out std_logic );end component prescaler;signal prescale_q: std_logic_vector(2 downto 0);signal clk_i: std_logic;signal prescale_event: std_logic;signal prescale_reset: std_logic;signal enq : std_logic;beginclkrise <= clkrise_i;clkfall <= clkfall_i;pr: prescaler port map ( clk => clk, rst => prescale_reset, prescale => prescale_q, event => prescale_event );genclk: process(clk)begin if rising_edge(clk) then if rst='1' or en='0' then spiclk <= cpol; else if clkrise_i='1' then spiclk<=not cpol; end if; if clkfall_i='1' then spiclk<=cpol; end if; end if; end if;end process; process(clk)begin if rising_edge(clk) then enq <= en; if rst='1' then prescale_q <= (others => '0'); running_q <= '0'; prescale_reset <= '0'; else if en='1' then prescale_reset<='0'; running_q <= '1'; if running_q='0' then prescale_q <= pres; prescale_reset<='1'; end if; else running_q <= '0'; end if; end if; end if;end process;process(clk)begin if rising_edge(clk) then if rst='1' then clkrise_i<='0'; clkfall_i<='0'; clk_i<='0'; else clkrise_i <= '0'; clkfall_i <= '0'; if en = '1' and enq = '0' then clkfall_i <= '1'; end if; if running_q='1' and en='1' then if prescale_event='1' then clk_i <= not clk_i; if clk_i='0' then clkrise_i <= '1'; else clkfall_i <= '1'; end if; end if; else clk_i <= '0'; end if; end if; end if;end process;end behave;
  13. Take over/release SPI using PPS

    Yes, I'd like to move the pins for the USPI to some other pins temporarily and then release them back to the original pins.
  14. Hello All I'm trying to share the USPI block between different hardware so I've written two functions to take control of the SPI and release it again. But it seems that the release does not work properly. Do I have to add/change something to make the SPI release properly from my assigned pins? Regards Kalle void takeSPI(){ //Relinquish control of PPS pins first pinModePPS(SDIPIN, LOW); pinModePPS(SCKPIN, LOW); pinModePPS(SDOPIN, LOW); //Assign our spi mode and pins USPICTL = BIT(SPICP2) | BIT(SPIEN) | BIT(SPIBLOCK) ; outputPinForFunction(ENC_SDI, IOPIN_USPI_MOSI); pinModePPS(ENC_SDI, HIGH); pinMode(ENC_SDI, OUTPUT); outputPinForFunction(ENC_CLK, IOPIN_USPI_SCK); pinModePPS(ENC_CLK, HIGH); pinMode(SCKPIN, OUTPUT);}void releaseSPI(){ //Relinquish control of PPS pins first pinModePPS(ENC_SDI, LOW); pinModePPS(ENC_CLK, LOW); USPICTL=BIT(SPICP0)|BIT(SPICPOL)|BIT(SPISRE)|BIT(SPIEN)|BIT(SPIBLOCK)|0x0E; outputPinForFunction( SDIPIN, IOPIN_USPI_MOSI ); pinModePPS(SDIPIN,HIGH); pinMode(SDIPIN,OUTPUT); outputPinForFunction( SCKPIN, IOPIN_USPI_SCK); pinModePPS(SCKPIN,HIGH); pinMode(SCKPIN,OUTPUT); pinModePPS(CSPIN,LOW); pinMode(CSPIN,OUTPUT); inputPinForFunction( SDOPIN, IOPIN_USPI_MISO ); pinMode(SDOPIN,INPUT);}
  15. spi.vhd error?

    I agree that the signals look like they align good enough for the different SPI modes, but: I think that the data should be pushed out so that the MOSI data is already on the data line half a SCK cycle before the leading edge on mode 0,0 because if the data is pushed at the same time as SCK is driven high there will be racing conditions occuring when interfacing with external hardware.. I have attached the actual waveform captured with my logic analyzer as well as a template of how I thought that mode 0,0 should look Best Regards Kalle