bluesign2k

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About bluesign2k

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  1. bluesign2k

    The next generation Papilio - help me shape it.

    I don't know if this is the kind of thing you guys are on about (sorry if not), or maybe your already aware of it...? A while ago I was looking for info on implementing a z80 system on my Pro, I came across a guy's site (http://fpgabee.toptensoftware.com/) who had done almost exactly what I was aiming to do (or the core of it at least). While he started developing on a Nexys3 his final design was on a Xula2 which used SDRAM. However, in his code there is a SDRAM controller written by xess specifically for the SDRAM device they put on the Xula2 and a core he's written called "Z80RamController" which presents the interface of the SDRAM controller as a much simpler interface: data in, data out, address, read, write and wait signal. With minimal modification I managed to get it to work fine on the Pro with it's SDRAM and have tried it on a number of "experiments" (I won't go so far as calling them projects because really I'm just playing around with things and try to learn). Anyway, whether or not it's what your after, it was enough for me to use the SDRAM where I otherwise probably wouldn't, so maybe it'll help someone else too. I found the original files here: SdramCntl.vhd - https://bitbucket.org/toptensoftware/fpgabee/src/55503cba59bf885ec4ddb3ef6fb82a246942ea76/Hardware/XuLA_lib/SdramCntl.vhd?at=master Z80RamController.vhd - https://bitbucket.org/toptensoftware/fpgabee/src/55503cba59bf885ec4ddb3ef6fb82a246942ea76/Hardware/Xula2/Z80RamController.vhd?at=master While I don't have a complete copy of my altered version of the Z80RamContoller here at the moment, I have a note of what I changed in that file: from: ram_addr : in std_logic_vector(17 downto 0); -- 256Kto: ram_addr : in std_logic_vector(15 downto 0); -- 64Kand from: sdram : SdramCntlgeneric map( FREQ_G => 100.0, IN_PHASE_G => true, PIPE_EN_G => false, MAX_NOP_G => 10000, DATA_WIDTH_G => 16, NROWS_G => 8192, NCOLS_G => 512, HADDR_WIDTH_G => 24, SADDR_WIDTH_G => 13)port map...to: sdram : SdramCntlgeneric map( FREQ_G => 100.0, IN_PHASE_G => true, PIPE_EN_G => false, MAX_NOP_G => 10000, DATA_WIDTH_G => 16, NROWS_G => 4096, --8192, NCOLS_G => 256, --512, HADDR_WIDTH_G => 24, SADDR_WIDTH_G => 13, T_INIT_G => 200_000.0, -- min initialization interval (ns). T_RAS_G => 45.0, -- min interval between active to precharge commands (ns). T_RCD_G => 15.0, -- min interval between active and R/W commands (ns). T_REF_G => 64_000_000.0, -- maximum refresh interval (ns). T_RFC_G => 66.0, -- duration of refresh operation (ns). T_RP_G => 15.0, -- min precharge command duration (ns). T_XSR_G => 67.0 -- exit self-refresh time (ns).)port map...Oh, I just remembered that it took me a while to get the clocking right too. I can't remember what I found tricky, but this I what I got it working with. clock : entity work.clockingport map ( CLK_IN_32_000 => clk_32, CLK_OUT_8_000 => clk_8, CLK_OUT_40_000 => vga_clock, CLK_OUT_100_000 => sdram_clock, RESET => '0');sdram_clk_forward : ODDR2generic map(DDR_ALIGNMENT => "NONE", INIT => '0', SRTYPE => "SYNC")port map ( Q => SDRAM_CLK, C0 => sdram_clock, C1 => not sdram_clock, CE => '1', R => '0', S => '0', D0 => '0', D1 => '1');Chris
  2. bluesign2k

    The next generation Papilio - help me shape it.

    I love the idea of onboard HDMI, it's one of the reasons I grabbed a Pipistrello a while back. I assume you can put the socket on the bottom right, where A8-A15 would usually be on a Mega. I wouldn't worry about trying to make it fit Mega cases, particularly if it compromises functionality. FWIW, I'd also try to find better places for the mounting holes, whoever did the original placement for the Uno/Mega was an idiot... 3 of the holes can never be used as there's no room for a screw head and another requires a nylon screw unless you're happy with risking a short. +1 for BGA too if you can do it. If you then land up with spare IO, how about routing them to an FPC footprint on the underside of the board so that those that want/need to can add the extra connector?
  3. bluesign2k

    Bad USB cable for the Papilio.

    Jack, I just noticed this topic. I recently received my board with a black cable which was fit for the bin when it arrived. It caused headaches for this past week (see here: http://forum.gadgetfactory.net/index.php?/topic/1512-logicstart-7seg-display-current-question/?p=11184) because it worked well enough to power the FPGA but clearly had a high resistance. Being new to FPGAs I had assumed it was my code that was to blame until I discovered the problem. A friend of mine had his board arrive yesterday with a black cable in an identical looking bag, but the cables were visually different. Mine was much thinner and more flexible. Chris
  4. bluesign2k

    LogicStart 7seg display current question

    I finally managed to sort this out myself. Turns out that it was a hardware problem... with the USB cable that was shipped with the Papilio Pro. To be honest it felt pretty poor quality after seeing that my code worked fine a friend's Pro board that just arrived I figured something weird was going on. After trying various combinations, we found that the 5v net on the board was ~4.7v without any shield plugged in. With the shield plugged in and all LEDs and segments illuminated the the 5v net dropped to 3.2v... nice(!)
  5. bluesign2k

    LogicStart 7seg display current question

    I've recently bought a Papilio Pro along with the LogicStart Megawing as I've been meaning to get into FPGAs for a while. It's been fun working through Hamster's course/pdf guide but I'm now having problems with the 7 segments display. The problem I'm having is not getting them to light as I want, that's fine, but more that if I turn on 4 or more (3 if any of the other LEDs are also lit) segments simultaneously at a time on any one digit, it crashes the FTDI device and the PC can't see either of the Pro's ports. As soon as I go back to 2 or less segments lit, it re-connects. I am currently multiplexing all four digits (as in Hamster's eBook) and am just displaying the same on each digit based on the state of the 8 switches. I have tried clock speeds from directly using the on-board 32 MHz clock down to a few Hz... same result every time. I've also tried 4 different computers. FWIW, I notice that in the device manager, the root hub states that the device requires only 90 mA... which is surely cutting it a bit fine when using the 7 Segment display? I think it's pretty clear that its a current draw issue, but at the moment short of either using a separate supply to power the board or program the segments to be lit one at a time I'm stuck for solutions. Any ideas?