hi mkarlsson I have been able to extend the implementation on papilio pro to use 256k out of the fpga. That's not a big issue. To go beyond that the use of the on board ram is needed. There is another board from dream source lab that has a similar hardware ( https://github.com/DreamSourceLab?tab=repositories ) but a slightly different ram. They use a different protocol but are able to dump few mega samples without problem. Unfortunatly for Jack the stuff is written in verilog . one possibility with relatively low effort is to port that code to papilio pro.