MicroN8

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  1. MicroN8

    Looking for VHDL Code for Quickstart-Papilio_One_500K-v1.5.bit

    Wecome aboard aaremnair! Yes, starting out in Logic programming is one frustrating beast sometimes. Just don't get discouraged and give up. I don't really know enough to fully troubleshoot your problem but here is some things to verify. Make sure you have the device setting on XC3S500E and the correct package VQ100 (for the 500K board). The names between your vhdl file and ucf file must match, so it might be a good idea to make your ucf file in all caps since the compiler makes all lowercase letters caps when it builds the implementation file (not sure about this but it rules one more thing out). Also, just use SWITCH(0) the underscore might not work. I would just change the names you use in VHDL to match the UCF file you already downloaded this way to don't have to write a new ucf for every project. You can always use # to comment out a line in the ucf, but some are needed almost all the time, like the clock (but the PERIOD=31.25ns can be removed). The compilers are also picky about needing the top level set to your schematic or VHDL file. I select the option to allow unlocked LOC constraints otherwise the project will not build unless you use every pin in the ucf. This can hide some problems but it allows you to build a project that doesn't use every pin. Yes, you will get alot of warnings about trimmed locations and such. Turn the output bit stream on or you won't get a bit file. Also, check the clock settings if it is set to Jtag in Xilinx the bit file must go to the FPGA not the SPI flash in the papilio programmer as I recently found out. CClk can go to the SPI flash. Just put your bit file in the right papilio programmer box and select the destination and you should be good to go (don't worry about the empty file box bmm and hex). There are a ton of settings in Xilinx and if some are not right it won't work at all. If your still stuck post as much info as you can so people can help in a more focused way than this rambling post of mine. Hope something in this post helps you. Sorry, If I covered something you already checked. You seem to have a good idea of what you are doing, so good luck and post any updates on getting it working (like what you had to do) because I have noticed new members have the same problems over and over. So your post could save someone else from having to post the same problem.
  2. MicroN8

    JRR Tolken Ring

    Ok, this one works with spi flash. I programmed this one to use CClk instead of Jtag clock. That was why it wouldn't work. token_top.bit
  3. MicroN8

    JRR Tolken Ring

    I am not sure if this is the problem, but I left out the part about the loader. Put the file in the Taget .bit file box and where it says Write to: select FPGA from the drop-down menu. I don't know how to make a bit file that can use the spi flash. I didn't think anyone would want to use this bit file that way. I figured it was kind-of a "one and done" thing. After all, how many times can it be entertaining. One will probably do it. I would love to learn how to save the bit file to the board and have it work. Is there a tutorial on how to enable the spi flash programming? I use VHDL and the schematic drawings mostly. Is the spi flash only for the Zap code users? I will look around on the forum, someone must have posted something. Anyway, I hope the bit file will work for you now. If not just post again and I'll send you the project or something. Thanks for checking it out.
  4. MicroN8

    JRR Tolken Ring

    Sorry about the bad pun...I am taking a computer networking class this term and the teacher has said token ring about 20+ times in 9 class periods. So, I got to thinking about how to implement such a design with logic. I spent today reading Introduction to Digital Design and messing around with the new Aldec Active HDL I had to download (due to the student version expired 1-1-14). I got a token ring simulation working on the PapPro and logic start wing. Each switch represent a network connected to the ring. If the switch is up the network wants to transmit. When the led above the switch is on the network has the token and is transmitting. If the switch is down the token is passed quicker. The token is placed in the ring by the up joystick and pressing the joystick like a button resets the whole ring(without a token). I spent about 8 hours messing with this. It just looks like a glorified Larson scanner though (if all switches are up). Oh well. One interesting thing I learned from it is that if you time it right and put 2 or more tokens into the ring (by pressing up again) and all the switches are not up, one token can catch the other one and it gets destroyed or less often both tokens get destroyed. I don't know if this is how it would work in a real token network since they only have one token, maybe it is just a flaw in my design. I used lots of D flip flops, some pulse extenders and clippers, a clock divider with fast and slow output, and a lot of or and and gates. Check it out if you have the papilio pro, logic shield and papilio loader handy and want to see some flashing leds respond to switches. token_top.bit
  5. MicroN8

    Papilio Pro software ADC

    I found some code in VHDL by searching "free dac ip". Not sure if it works or if it will work for your application, but here it is. ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- The Free IP Project -- VHDL Free-DAC Core -- © 2000, The Free IP Project and David Kessner -- -- -- FREE IP GENERAL PUBLIC LICENSE -- TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION -- -- 1. You may copy and distribute verbatim copies of this core, as long -- as this file, and the other associated files, remain intact and -- unmodified. Modifications are outlined below. -- 2. You may use this core in any way, be it academic, commercial, or -- military. Modified or not. -- 3. Distribution of this core must be free of charge. Charging is -- allowed only for value added services. Value added services -- would include copying fees, modifications, customizations, and -- inclusion in other products. -- 4. If a modified source code is distributed, the original unmodified -- source code must also be included (or a link to the Free IP web -- site). In the modified source code there must be clear -- identification of the modified version. -- 5. Visit the Free IP web site for additional information. -- http://www.free-ip.com -- ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package free_dac_lib is component dac_ds generic (n_bits :integer); port (reset :in std_logic; clk :in std_logic; din :in std_logic_vector (n_bits-1 downto 0); dout :out std_logic ); end component; component dac_pwm generic (n_bits :integer); port (reset :in std_logic; clk :in std_logic; din :in std_logic_vector (n_bits-1 downto 0); dout :out std_logic ); end component; component dac_pwm2 generic (n_bits :integer); port (reset :in std_logic; clk :in std_logic; period :in std_logic_vector (n_bits-1 downto 0); width :in std_logic_vector (n_bits-1 downto 0); dout :out std_logic ); end component; end package; ----------------------------------------------------------------------------- -- First Order Delta Sigma DAC ----------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library work; use work.free_dac_lib.all; entity dac_ds is generic (n_bits :integer); port (reset :in std_logic; clk :in std_logic; din :in std_logic_vector (n_bits-1 downto 0); -- Signed integer dout :out std_logic ); end dac_ds; architecture arch_dac_ds of dac_ds is signal error :std_logic_vector (n_bits+1 downto 0); -- Error accumulator is 2 bits larger constant zeros :std_logic_vector (n_bits-1 downto 0) := (others=>'0'); begin process (reset, clk, din) variable val :std_logic_vector (n_bits+1 downto 0); begin if reset='1' then error <= (others=>'0'); dout <= '0'; elsif clk'event and clk='1' then -- val := din + error; din is sign extended to nbits+2 val := (din(din'high) & din(din'high) & din) + error; if val(val'high) = '0' then dout <= '1'; error <= val + ("11" & zeros); else dout <= '0'; error <= val + ("01" & zeros); end if; end if; end process; end arch_dac_ds; ----------------------------------------------------------------------------- -- DAC via Pulse Width Modulation ----------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library work; use work.free_dac_lib.all; entity dac_pwm is generic (n_bits :integer); port (reset :in std_logic; clk :in std_logic; din :in std_logic_vector (n_bits-1 downto 0); -- unsigned integer dout :out std_logic ); end dac_pwm; architecture arch_dac_pwm of dac_pwm is signal period_counter :std_logic_vector (din'range); signal width_counter :std_logic_vector (din'range); signal last :std_logic; signal last_d :std_logic; signal width_flag :std_logic; constant zeros :std_logic_vector (n_bits-2 downto 0) := (others=>'0'); begin -- The period counter process (reset, clk) begin if reset='1' then period_counter <= (others=>'1'); elsif clk'event and clk='1' then period_counter <= period_counter - 1; end if; end process; -- The last cycle flag. Active on the last cycle of the period process (reset, clk) begin if reset='1' then last <= '0'; last_d <= '0'; elsif clk'event and clk='1' then last_d <= last; if period_counter = (zeros & "1") then last <= '1'; else last <= '0'; end if; end if; end process; -- The width coutner process (reset, clk) begin if reset='1' then width_counter <= (others=>'0'); width_flag <= '0'; elsif clk'event and clk='1' then if width_counter = (zeros & "0") then width_flag <= '1'; else width_flag <= '0'; end if; if last='1' then width_counter <= din; else width_counter <= width_counter-1; end if; end if; end process; -- The output process (reset, clk) begin if reset='1' then dout <= '0'; elsif clk'event and clk='1' then if last='1' then dout <= '1'; elsif width_flag='1' then dout <= '0'; end if; end if; end process; end arch_dac_pwm; ----------------------------------------------------------------------------- -- DAC via Pulse Width Modulation - with variable pulse frequency ----------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library work; use work.free_dac_lib.all; entity dac_pwm2 is generic (n_bits :integer); port (reset :in std_logic; clk :in std_logic; period :in std_logic_vector (n_bits-1 downto 0); -- unsigned width :in std_logic_vector (n_bits-1 downto 0); -- unsigned dout :out std_logic ); end dac_pwm2; architecture arch_dac_pwm2 of dac_pwm2 is signal period_counter :std_logic_vector (period'range); signal width_counter :std_logic_vector (period'range); signal last :std_logic; signal last_d :std_logic; signal width_flag :std_logic; constant zeros :std_logic_vector (n_bits-2 downto 0) := (others=>'0'); begin -- The period counter process (reset, clk) begin if reset='1' then period_counter <= (others=>'1'); elsif clk'event and clk='1' then if last='1' then period_counter <= period; else period_counter <= period_counter - 1; end if; end if; end process; -- The last cycle flag. Active on the last cycle of the period process (reset, clk) begin if reset='1' then last <= '0'; last_d <= '0'; elsif clk'event and clk='1' then last_d <= last; if period_counter = (zeros & "1") then last <= '1'; else last <= '0'; end if; end if; end process; -- The width coutner process (reset, clk) begin if reset='1' then width_counter <= (others=>'0'); width_flag <= '0'; elsif clk'event and clk='1' then if width_counter = (zeros & "0") then width_flag <= '1'; else width_flag <= '0'; end if; if last='1' then width_counter <= width; else width_counter <= width_counter-1; end if; end if; end process; -- The output process (reset, clk) begin if reset='1' then dout <= '0'; elsif clk'event and clk='1' then if last='1' then dout <= '1'; elsif width_flag='1' then dout <= '0'; end if; end if; end process; end arch_dac_pwm2; ----------------------------------------------------------------------------- -- -----------------------------------------------------------------------------
  6. MicroN8

    Variable Speed Clock

    It really depends on how you want to do it. In Zap IDE or Xilinx IDE (C, verilog or VHDL) and how you want it to work with hardware (i.e. led, 7 segment or serial monitor). I worked on a bit file in Xilinx that will blink an led. If you have a papilio pro and a logic start you can use it !clockdivider_top.bit. Swich 0 must be on and pressing joy select will go from 50 Hertz to about 0.4 Hertz in 8 steps. I used 2 clock dividers, 2 delays, a counter and a 8 to 1 mux. Zap IDE would probably be easier. Arduino Cookbook is a great place to start. Go to http://examples.oreilly.com/0636920022244/ and download the files. Look at sections 3.2 +&- values, 5.1 switches, and 12.4 on setting up an actual clock (for the serial monitor). Arduino.cc is OK but lacks alot of details. I am not sure if the example codes can just be copy pasted into zap, but it is a start. If you get stuck just post again (and give lots of details). Good Luck
  7. MicroN8

    PRO UCF file

    After posting that I don't use xilinx ise (see above), I thought "Am I missing something by not using it?". So I looked on the forum and found the post about redirecting the shortcut in windows 8 to the 32bit version instead of the 64bit version. Now, as if by magic, I can use xilinx ise. Aldec active HDL is cool, but now I feel like I can get the full FPGA experience. This is such a great forum and just the place to help reduce the learning curve on FPGA development. My first bit file from xilinx ise is "Hello Papilio" (since world doesn't work on 7 seg display) scrolling on the Logic Start and Papilio Pro. Thanks again Papilio forum. The great community here ( Mr. Gassett, alvieboy and hamster especially) is what convinced me to buy a papilio board. hello_papilio.bit
  8. MicroN8

    PRO UCF file

    I don't use xilinx ise, but in the one I use the box Allow Unmatched LOC Constraints under translate must be checked or it will not implement the design. Like you said I will get an error for every pin. In addition the jtag clock must be used for startup and I have to check a box to generate a bit file. This might not apply to Xilinx ise, not really sure. Sorry, I can't be more specific.
  9. MicroN8

    First design... and first question!

    Just got my logic start (for my papilio pro) today and I got my first working bit file created. It is a simple 4 bit adder (switch0 to 3 and 4 to 7). The switches control segment q3 and q4. q2 is a carry bit and q1 is the sum. joystick press is a reset and shows that the segments are multiplexed. Only issue that bothered me is the UCF file had to be modified by taking out <pullup> on TX and Flash_SO to work with Aldec ActiveHDL student version. What will this do? I am new to FPGA design, and I am worried with others designs and no pullups i may fry some leds or worse, damage the chip. I also had to remove period=31.25ns from clk. Thanks for having such a great product and forum. edit -- commented out unused pins in ucf file sum_carrybit_add4_add4.bit